Design Of All-digital Phase-locked Loop Research Articles

ALL-DIGITAL PHASE LOCKED LOOP (ADPLL) TOPOLOGIES FOR RFID SYSTEM APPLICATION: A REVIEW

An all-digital phase locked loop (ADPLL)-based local oscillator (LO) of RF transceiver application such as radio-frequency identification (RFID) system has gained popularity by accessing the benefits in complementary metal-oxide semiconductor (CMOS) process technology. This paper reviews some state-of-art of the ADPLL structures based on their applications and analyses its major implementation block, which is the digital-controlled oscillator (DCO). The DCO is evaluated based on its CMOS scaling and its performance in ADPLL, such as the power consumption, the chip area, the frequency range, the supply voltage, and the phase noise. Based on the review, the reduction in CMOS scaling decreases the transistor size in ADPLL design which leads to a smaller area and a low power dissipation. The combination of the time-to-digital (TDC) and the digital-to-time converter (DTC) that is used as the phase-frequency detector (PFD) in ADPLL is proposed to reduce the power and phase noise performance due to their high linearity design. The delay cell oscillator is found to consume more power at higher operating frequency, but it has an advantage of having less complexity and consuming less power and area in the circuit compared to the LC tank oscillator. For future work, it is recommended that an ADPLL-based LO of RFID transceiver with lowest voltage supply implementation is chosen and the use of the TDC-less as the PFD is selected due to its small area. While for the DCO, the delay cell will be designed due to its simpler implementation and occupy small area.

A CMOS implementation of controller based all digital phase locked loop (ADPLL)

PurposeBiomedical radio frequency (RF) transceivers require miniaturized forms with long battery life and low power consumption. The medical implant communication service (MICS) band in the frequency range of 402–405 MHz is widely used for medical RF transceivers because the MICS band signals have reasonable propagation characteristics and are suited to achieve good results. The implementation of the RF front-end for medical devices has many challenges as these dictate low power consumption. In particular, phase-locked loop is one of the most critical blocks of the RF front-end. The purpose of this paper is to the design of controller-based all-digital phase-locked loop (ADPLL) in a 45 nm CMOS process.Design/methodology/approachInitially, an open-loop architecture phase frequency detector (PFD) is designed. Then based on the concept of differential buffer, a differential ring oscillator (RO) is built using capacitive boosting technique. After that, the frequency controller block is built by proper mathematical modeling that does the job of loop filter, which behaves like a phase interpolator. Frequency controller block has tuning register block, tuning word register. The tuning block is built using the Metal Oxide Semiconductor (MOS) caps. Finally, the integration of all the blocks is done and the ADPLL architecture that locks at 402 MHz is achieved.FindingsThe designed PFD is dead zone free that operates at 1 GHz. The differential RO oscillates at 495 MHz. The proposed ADPLL operates at 402 MHz with measured phase noise of −98.36 at 1-MHz offset. This ADPLL exhibits rms jitter of 4.626 ps with a total power consumption of 216.5 µW.Research limitations/implicationsA time to digital converter (TDC)-less controller-based low power ADPLL covering the MICS frequency band for biomedical applications has been designed in 45 nm/0.68 V CMOS technology. The ADPLL proposed in this draft uses differential oscillator with capacitively boosted technique which reduced the operating voltage to as low as 0.68 V. This ADPLL has a bandwidth of 20 kHz and works at reference frequency of 20 MHz consumed power of 216.5 µW, while generating an output frequency of 402 MHz. The tuning range is from 375 to 428 MHz. With the phase noise of −98.36 dbc/Hz at 1 MHz, a frequency controller block replaces the usage of TDC.Social implicationsThe designed ADPLL will definitely pave way to greater research arena in the field of biomedical field. This ADPLL is a unique combination that combines electronics and biomedical field. The designed ADPLL is itself a broader application to biomedical field that will have a positive impact on the society.Originality/valueThe implementation of open-loop PFD and RO using the capacitive boosting technique is a unique combination. This is comprehended well with frequency controller block that eliminates the usage of TDC and behaves as phase interpolator. The entire design of ADPLL which suits the application of MICS band of frequency has been designed carefully to work at low power.

A Robust and Efficient Fault-Resilient RadHard ADPLL

The high pace emergence in semiconductor technologies and associated application demands have revitalized industries to explore power efficient, stable and fault tolerant digital communication solutions, particularly for time critical applications operating at higher frequency ranges. Thus strengthening low cost CMOS digital design with Radiation Hardened by Design (RHBD) approach can be of paramount significance compared against the high cost Radiation Hard by Process (RHBP) approach. With this motivation, in this paper a novel and robust All-Digital-Phase Locked Loop (ADPLL) design has been developed for frequency synthesis. Our ADPLL design model encompasses multiple novelties and contributions including Feedback-Divider-Less-Counter (FDLC) based ADPLL, predictive phase-frequency detection (PFD), enhanced Time to Digital Converter (TDC) to detect next-edge occurrence of the reference clock that reduces locking period and complexity. The predictive PFD applies a phase-prediction scheme that delays the clock-edges of the reference frequency with a calibrated amount that it always aligned towards the expected frequency clock edge. It makes TDC to be narrow enough to cover the reference and oscillator jitter. Our proposed ADPLL design applied a narrow range converter (TDC) that assist phase-error prediction, correction and phase detection. The reference clock delay facilitates accurate timing relationship estimation with the variable frequency and hence performs retuning of the variable clock to reduce locking period and reduce noise. The ADPLL design has exhibited satisfactory performance for the frequency synthesis with reference frequency of 20MHz and the synthesis frequency of 2.4 GHz meeting radiation hardened features. The simulation results has revealed that the proposed Rad Hard ADPLL design can be a potential solution for space communication systems by maintaining low jitter of 340ps and power consumption of 371.7mW, as the narrow range TDC designed can detect sample radiation induced impulse noise of 20ns, 1mV and correct it.

Design of all-digital phase-locked loop based on pipeline technology

Design of all-digital phase-locked loop based on pipeline technology

Energy Efficient All-Digital Phase Locked Loop Architecture Design on High Resolution Fast Clocking Time to Digital Converter (TDC) Using Model Prescient Control (MPC) Technique

Phase locked loops (PLLs) are utilized as a part of clock recovery and frequency synthesis. Entirely digital PLLs are more reasonable for the solid execution with different circuits contrasted with the customary usage of the PLLs. The all-digital PLLs are additionally autonomous of process varieties and can be efficiently ported to various innovations. In this work displays the plan of an all-digital phase locked loop (ADPLL) utilizing a quick timing based time to digital converter (TDC) and a model prescient control (MPC) method. General outline criteria are condensed for the all-digital usage in contrast with the common methodologies and simple executions. The outline has been actualized utilizing 0.18 μm CMOS innovation. The ADPLL can work in the frequency run between 215 and 350 MHz the ADPLL has a 1.768 μs bolt time off. This work displays the ADPLL configuration utilizing tanner and examination the execution of parameters. Power is point by point in tanner. A subtle element of the fundamental blocks of an ADPLL is talked about. In this work, the lessening of highest frequency, power, transient examination and delay is spoken of the outcome is thought about. Its simulation comes about utilizing tanner tool are additionally talked about. The proposed ADPLL design dynamic phase frequency locator with MPC_TDC most extreme power utilization is 4.653 mW and the proposed ADPLL with MPC_TDC was mainly used in communication applications.

ANALYSIS OF FREQUENCY SYNTHESISERS FOR MULTISTANDART WIRELESS TRANSCEIVER / DAŽNIO SINTEZATORIŲ DAUGIASTANDARČIAMS BEVIELIO RYŠIO SIŲSTUVAMS IR IMTUVAMS ANALIZĖ

Frequency synthesiser is one of most important blocks in wire-less transceiver. Generally phase locked loop (PLL) is used as frequency synthesiser in multistandart wireless transceivers. Two main structures of PLL are conventional (mixed, charge pump) PLL and All-Digital PLL. Newest works, related to design of conventional PLLs, are oriented to minimise power consumption and chip size, increase loop bandwidth and decrease frequency locking time. Main focus of All-Digital PLLs design is to reduce quantisation noise. New figure of merit (FOM) is proposed to compare frequency synthesisers of different type. This function depends on all main parameters of frequency synthesizer for multistandart transceiver: phase noise, operation frequency, frequency tuting range, power dissipation, used area of silicon. Used CMOS technology is also assessed in proposed FOM. From the calsulated FOM value for newest published frequency synthesisers it is seen, that in nanometric technologies All-Digital frequency synthesisers are superior to conventional synthesisers. Although, performance of conventional frequency synthesisers, implemented in larger technologies (0.18 µm ir 0.13 µm), is comparable or better than performance of All-Digital synthesisers. Dažnio sintezatorius yra vienas iš svarbiausių blokų bevielio ryšio siųstuvuose-imtuvuose. Kaip dažnio sintezatorius daugiastandarčiams bevielio ryšio siųstuvams ir imtuvams dažniausiai yra naudojama fazės derinimo kilpa (FDK). Dvi pagrindinės FDK struktūros yra klasikinė (mišri, krūvio pompos) ir visiškai skaitmeninė fazės derinimo kilpa. Naujausiuose darbuose, susijusiuose su klasikinės FDK projektavimu, siekiama mažinti galią ir plotą, dažnio suderinimo trukmę, platinti praleidžiamų dažnių ruožą. Pagrindinis dėmesys projektuojant visiškai skaitmenines FDK skiriamas kvantavimo triukšmui mažinti. Įvairių struktūrų ir tipų dažnio sintezatoriams palyginti yra siūloma nauja kokybės funkcija (FOM). Ši funkcija priklauso nuo visų pagrindinių sintezatoriaus, tinkančio daugiastandarčiams siųstuvams-imtuvams, parametrų: fazinio triukšmo, darbinio dažnio, dažnio perderinimo ruožo pločio, vartojamosios galios, luste užimamo ploto. Taip pat įvertinama naudojama KMOP technologija. Iš apskaičiuotų kokybės funkcijos rezultatų naujausiems publikuotiems dažnio sintezatoriams matyti, kad nanometrinėse technologijose visiškai skaitmeninės struktūros dažnio sintezatoriai yra pranašesni už klasikinius, tačiau didesnėse (0,18 μm ir 0,13 μm) technologijose įgyvendinti klasikiniai dažnio sintezatoriai yra lygiaverčiai arba pranašesni už visiškai skaitmeninius sintezatorius.

A Fast Locking All-Digital Phase-Locked Loop via Feed-Forward Compensation Technique

A fast locking all-digital phase-locked loop (ADPLL) via feed-forward compensation technique is proposed in this paper. The implemented ADPLL has two operation modes which are frequency acquisition mode and phase acquisition mode. In frequency acquisition mode, the ADPLL achieves a fast frequency locking via the proposed feed-forward compensation algorithm. In phase acquisition mode, the ADPLL achieves a finer phase locking. To verify the proposed algorithm and architecture, the ADPLL design is implemented by SMIC 0.18-μm 1P6M CMOS technology. The core size of the ADPLL is 582.2 μm * 343 μm. The frequency range of the ADPLL is from 4 to 416 MHz. The measurement results show that the ADPLL can achieve a frequency locking in two reference cycles when locking to 376 MHz. The corresponding power consumption is 11.394 mW.

Built-in Self-Calibration Circuit for Monotonic Digitally Controlled Oscillator Design in 65-nm CMOS Technology

This brief presents a built-in self-calibration (BISC) circuit to correct nonmonotonic responses in a digitally controlled oscillator (DCO) with a cascading structure. Generally speaking, a cascading DCO structure has the advantages of low power consumption and a small chip area. Nevertheless, when a subfrequency band is changed, an overlap region between subfrequency bands causes a large phase error and cycle-to-cycle jitter in an output clock. The proposed BISC circuit can reduce this problem; thus, it is very suitable for a low-power all-digital phase-locked loop design in system-on-a-chip applications. The proposed DCO, implemented with a standard performance 65-nm complementary metal-oxide-semiconductor process, can output frequency ranges from 47.8 to 538.7 MHz. The total power consumption of the DCO with a calibration circuit is 0.142 mW at 58.7 MHz and 0.205 mW at 481.6 MHz.

A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation Algorithm

This brief presents a frequency estimation algorithm (FEA) for an all-digital phase-locked loop (ADPLL) instead of the traditional binary frequency-searching algorithm. Based on the proposed FEA and a new fast-lock scheme, a fast-lock engine is designed to improve the lock-in time of an ADPLL design with two referenced clock cycles. An implementation of the proposed ADPLL design is realized by utilizing United Microelectronics Corporation (UMC) 0.18-μm 1P6M CMOS technology with a core area of 300 × 250 μm2, consisting of an acceptable input reference clock ranging from 220 kHz to 8 MHz. The ADPLL design has a frequency range of 28-446 MHz with an 8.8-ps digitally controlled oscillator resolution. Moreover, the peak-to-peak jitter of the ADPLL achieves 70 ps, respectively.

Design of ADPLL for both large lock-in range and good tracking performance

This paper describes a new all-digital phase locked loop (ADPLL). The proposed ADPLL contains a frequency offset estimator and a phase-error estimator. Thereby, it can provide both large lock-in range and good tracking performance. Furthermore, it does not suffer severely from the phase jitter due to the quantization effect of the numerically controlled oscillator. In addition to some mathematical performance analysis, various simulation and experimental results are also presented to illuminate further the practical use and the excellent performance of the proposed ADPLL.