All-digital Frequency Research Articles

A low power all-digital frequency locked loop with resource-efficient frequency detector and hysteresis lock detector

A low power all-digital frequency locked loop with resource-efficient frequency detector and hysteresis lock detector

A VLSI Digital Circuit Platform for Performing Deterministic Stochastic Computing in the Time Dimension Using Fraction Operations on Rational Numbers

Stochastic computing (SC) is a method of expressing values in streams of random bits and performing computation with bitwise operations on the streams. Recently, it was found that SC can be conducted on deterministic bitstreams where a numerical value is represented uniformly by sections of 1s and 0s. This leads to deterministic SC, where the computing result can be 100% accurate. However, at the current stage, its circuit implementation has not reached the level of practicality. Moreover, the expressible values for operands are theoretically limited. An all-digital frequency synthesizer, time-average-frequency direct period synthesis (TAF-DPS), is proposed here as a hardware platform for performing deterministic SC in the time dimension. The TAF-DPS is used as a rational-number-to-time converter (RNTC), transforming a rational number into an electrical waveform. Waveforms of unique frequencies and duty cycles are then generated according to the operand values. Instead of digital bitwise operations, each computation is carried out in the time regime on waveforms. Hence, it can be regarded as an “analog-like” logical operation. This RNTC-based time-domain operation opens up a subfield of SC: rational number stochastic computing (RN-SC). In RN-SC, fraction computation can be executed with logic gates, and the result is 100% accurate. The enabling factor is the improvement in resource utilization since the time dimension is exploited more efficiently. With this extra resource of time, expansion of the scope of SC is expected. In this article, the working principle is elucidated, and the circuit is discussed. Furthermore, a field-programmable gate array (FPGA) prototype is created to validate this platform for SC. The aim of this work is to create a practical tool for broadening the use of SC.

Chip Design of an All-Digital Frequency Synthesizer with Reference Spur Reduction Technique for Radar Sensing

5.2-GHz all-digital frequency synthesizer implemented proposed reference spur reducing with the tsmc 0.18 µm CMOS technology is proposed. It can be used for radar equipped applications and radar-communication control. It provides one ration frequency ranged from 4.68 GHz to 5.36 GHz for the local oscillator in RF frontend circuits. Adopting a phase detector that only delivers phase error raw data when phase error is investigated and reduces the updating frequency for DCO handling code achieves a decreased reference spur. Since an all-digital phase-locked loop is designed, the prototype not only optimized the chip dimensions, but also precludes the influence of process shrinks and has the advantage of noise immunity. The elements of novelties of this article are low phase noise and low power consumption. With 1.8 V supply voltage and locking at 5.22 GHz, measured results find that the output signal power is −8.03 dBm, the phase noise is −110.74 dBc/Hz at 1 MHz offset frequency and the power dissipation is 16.2 mW, while the die dimensions are 0.901 × 0.935 mm2.

An all-digital frequency tunable IR-UWB transmitter with an approximate 15th derivative Gaussian pulse generator

This work presents a new frequency-tunable, OOK–modulated, impulse-radio ultra-wideband (IR-UWB) transmitter, where approximate 15th derivative Gaussian pulses are produced by a monopulse-synthesis pulse generator. The center frequency of our output UWB pulses can be easily adjusted between 4 and 9 GHz by controlling delay time. Thus, the whole UWB frequency band from 3.1 to 10.6 GHz can be covered and utilized. Since the proposed monopulse-synthesis pulse generator already includes a pulse shaping function, RF bandpass filters are not required, thus realizing the extremely low complexity and small circuit area. The proposed IR-UWB transmitter has been implemented and fabricated in a standard 0.18 μm CMOS 1p6m process. The power supply voltage is 1.8 V and the targeted data rate is 31.25 Mbps. Chip measurement results show that the power spectrum density conforms to the FCC spectrum masks, and the peak-to-peak voltage of output UWB pulses is 56 mV. In addition, the core area of the chip is 0.02 mm2, the measured frequency tuning range is 3.1–10.6 GHz, and the measured energy dissipation is only 12.5 pJ/bit. Compared to the state-of-the-art designs in the literature, the chip area and tunable frequency range are improved by at least 33% and 53%, respectively.

Structure of All-Digital Frequency Synthesiser for IoT and IoV Applications

In recent years number of Internet of Things (IoT) services and devices is growing and Internet of Vehicles (IoV) technologies are emerging. Multiband transceiver with high performance frequency synthesisers should be used to support a multitude of existing and developing wireless standards. In this paper noise sources of an all-digital frequency synthesiser are discussed through s-domain model of frequency synthesisers, and the impact of noise induced by main blocks of synthesisers to the overall phase noise of frequency synthesisers is analysed. Requirements for time to digital converter (TDC), digitally controlled oscillator (DCO) and digital filter suitable for all-digital frequency synthesiser for IoT and IoV applications are defined. The structure of frequency synthesisers, which allows us to meet defined requirements, is presented. Its main parts are 2D Vernier TDC based on gated ring oscillators, which can achieve resolution close to 1 ps; multi core LC-tank DCO, whose tuning range is 4.3–5.4 GHz when two cores are used and phase noise is −116.4 dBc/Hz at 1 MHz offset from 5.44 GHz carrier; digital filter made of proportional and integral gain stages and additional infinite impulse response filter stages. Such a structure allows us to achieve a synthesiser’s in-band phase noise lower than −100 dBc/Hz, out-of-band phase noise equal to −134.0 dBc/Hz and allows us to set a synthesiser to type-I or type-II and change its order from first to sixth.

A 2.4-GHz Super-Regenerative Transceiver With Selectivity-Improving Dual Q-Enhancement Architecture and 102- $\mu \text{W}$ All-Digital FLL

A multichannel super-regenerative transceiver with a selectivity-improving dual Q-enhancement architecture and a 102- $\mu \text{W}$ all-digital frequency-locked loop (FLL) is presented for bio-signal sensor nodes covering the 2.36–2.4-GHz medical band and 2.4-GHz industrial-scientic-medical (ISM) band. The conventional super-regenerative receiver suffers from the weak selectivity, and its performance is deteriorated in proportion to an increase of the data rate. The proposed receiver implements dual Q-enhancement operation of the low-noise amplifier (LNA) and super-regenerative oscillator (SRO) and improves the interferer rejection without data rate dependence. For channel frequency synthesis, an all-digital FLL is integrated. The digital fine-tuning method obviates the control voltage discharging issue of oscillator in analog phase locked loop (PLL) during SRO quenching operation, and the simplified all-digital frequency loop reduces the frequency synthesizer power in the ultralow-power sensor nodes. Implemented in 90-nm CMOS technology, the proposed transceiver occupies an effective die size of 1.81 mm2 and achieves an sensitivity of −82 dBm at 1-Mb/s/ $10^{-3}$ bit error rate (BER) and interference selectivity of 32 dB at a 1-Mb/s/10-MHz offset while consumping $102~\mu \text{W}$ at the all-digital FLL and 0.93/2.37 nJ/b at receiver/transmitter, respectively.

A 0.9–5.8-GHz Software-Defined Receiver RF Front-End With Transformer-Based Current-Gain Boosting and Harmonic Rejection Calibration

A 0.9–5.8-GHz receiver RF front-end (RFE) integrating a dual-band low-noise transconductance amplifier (LNTA), a passive harmonic-rejection (HR) down-conversion mixer, and an all-digital frequency synthesizer for software-defined radios are presented. A switchable three-coil transformer acting as the interface between the LNTA and the mixer features current-gain boosting in addition to wideband operation. Automatic local oscillator phase-error detection and calibration circuitry is implemented for the mixers to achieve high HR ratio (HRR). Fabricated in 65-nm CMOS, the RFE measures the noise figure between 2.9 and 3.8 dB, the third-order input intercept point (IIP3) between −1.6 and −12.8 dBm, the third-order HRR of 81 dB, and the fifth-order HRR of 70 dB, while consuming 66–82 mA from a 1.2-V supply and occupying a chip area of 4.2 mm2.

Increasing a Resolution of Time to Digital Converter

Time to digital converter (TDC) is one of the main blocks of all-digital frequency synthesizer (FS), where it is used as phase detector. The output of TDC is digital, therefore it introduces quantization noise to the output of FS. The resolution of TDC has to be increased, to improve phase noise level at the output of FS. It can be achieved by improving CMOS technology or structure of the TDC. The simplest TDC is based on inverter delay line. Its resolution is inversely proportional to the time interval, which can be measured with such TDC, i.e. delay time of the inverter. Decreasing of this delay is essence of technological increasing of TDC’s resolution. In this work the dependency of inverter delay on technological parameters is shown and its value is calculated in 65 nm CMOS technology. Calculations show, that in this technology delay time of the inverter can vary from 7 ps to 54 ps. If the design is restricted to the usage of specific CMOS technology, in which inverter’s delay does not ensure needed noise level at the output of FS, structure of the TDC needs to be improved. The aim of this improvement is to measure time interval smaller than inverter’s delay. Some of the TDC structures, which can measure sub-inverter delay time, are reviewed in this work: TDC – Vernier delay line, TDC – 2D Vernier plane, stochastic, ring and multistage TDCs.

All-Digital Galvanically-Coupled BCC Receiver Resilient to Frequency Misalignment.

It is promising for wearable devices to go to a miniature size to alleviate the load of human body. One way to miniaturize the communication nodes on human body is to remove the bulky components such as antenna and crystal. Galvanically-coupled body channel communication (GC-BCC) has a great advantage over conventional wireless communications in reducing the size of wearable devices because it reuses the monitoring electrodes for signal transmission in place of antennas. To remove the crystal as well, the receiver must be immune to different types of frequency misalignments. This paper presents a GC-BCC receiver based on low power all-digital Gaussian frequency shift keying (GFSK) demodulation and clock-data recovery (CDR). A carrier tracking technique is proposed to detect and automatically adapt to the misalignment of carrier frequency. In addition, we also propose a circle-index CDR circuit to deal with the inaccuracy or drift of the clock frequency. The proposed circuit is implemented with 0.18 μm CMOS technology, and it operates at 200 kHz with a BFSK/GFSK modulation index of 1.0. Measured results show that the chip consumes 0.53 mA at a data rate of 100 kb/s. At a 10 cm body channel length, the GC-BCC receiver can tolerate a carrier misalignment up to [Formula: see text] and a clock error up to [Formula: see text], while keeping the bit error rate (BER) below 0.1%.

Single-Bit All-Digital Frequency Synthesis Using Homodyne Sigma-Delta Modulation.

All-digital frequency synthesis using bandpass sigma-delta modulation to achieve spectrally clean single-bit output is presented and mathematically analyzed resulting in a complete model to predict the stability and output spectrum. The quadrature homodyne filter architecture is introduced resulting in efficient implementations of carrier-frequency-centered bandpass filters for the modulator. A multiplierless version of the quadrature homodyne filter architecture is also introduced to reduce complexity while maintaining a clean in-band spectrum. MATLAB and SIMULINK simulation results present the potential capabilities of the synthesizer architectures and validate the accuracy of the developed theoretical framework.

ANALYSIS OF FREQUENCY SYNTHESISERS FOR MULTISTANDART WIRELESS TRANSCEIVER / DAŽNIO SINTEZATORIŲ DAUGIASTANDARČIAMS BEVIELIO RYŠIO SIŲSTUVAMS IR IMTUVAMS ANALIZĖ

Frequency synthesiser is one of most important blocks in wire-less transceiver. Generally phase locked loop (PLL) is used as frequency synthesiser in multistandart wireless transceivers. Two main structures of PLL are conventional (mixed, charge pump) PLL and All-Digital PLL. Newest works, related to design of conventional PLLs, are oriented to minimise power consumption and chip size, increase loop bandwidth and decrease frequency locking time. Main focus of All-Digital PLLs design is to reduce quantisation noise. New figure of merit (FOM) is proposed to compare frequency synthesisers of different type. This function depends on all main parameters of frequency synthesizer for multistandart transceiver: phase noise, operation frequency, frequency tuting range, power dissipation, used area of silicon. Used CMOS technology is also assessed in proposed FOM. From the calsulated FOM value for newest published frequency synthesisers it is seen, that in nanometric technologies All-Digital frequency synthesisers are superior to conventional synthesisers. Although, performance of conventional frequency synthesisers, implemented in larger technologies (0.18 µm ir 0.13 µm), is comparable or better than performance of All-Digital synthesisers. Dažnio sintezatorius yra vienas iš svarbiausių blokų bevielio ryšio siųstuvuose-imtuvuose. Kaip dažnio sintezatorius daugiastandarčiams bevielio ryšio siųstuvams ir imtuvams dažniausiai yra naudojama fazės derinimo kilpa (FDK). Dvi pagrindinės FDK struktūros yra klasikinė (mišri, krūvio pompos) ir visiškai skaitmeninė fazės derinimo kilpa. Naujausiuose darbuose, susijusiuose su klasikinės FDK projektavimu, siekiama mažinti galią ir plotą, dažnio suderinimo trukmę, platinti praleidžiamų dažnių ruožą. Pagrindinis dėmesys projektuojant visiškai skaitmenines FDK skiriamas kvantavimo triukšmui mažinti. Įvairių struktūrų ir tipų dažnio sintezatoriams palyginti yra siūloma nauja kokybės funkcija (FOM). Ši funkcija priklauso nuo visų pagrindinių sintezatoriaus, tinkančio daugiastandarčiams siųstuvams-imtuvams, parametrų: fazinio triukšmo, darbinio dažnio, dažnio perderinimo ruožo pločio, vartojamosios galios, luste užimamo ploto. Taip pat įvertinama naudojama KMOP technologija. Iš apskaičiuotų kokybės funkcijos rezultatų naujausiems publikuotiems dažnio sintezatoriams matyti, kad nanometrinėse technologijose visiškai skaitmeninės struktūros dažnio sintezatoriai yra pranašesni už klasikinius, tačiau didesnėse (0,18 μm ir 0,13 μm) technologijose įgyvendinti klasikiniai dažnio sintezatoriai yra lygiaverčiai arba pranašesni už visiškai skaitmeninius sintezatorius.

Spurs-Free Single-Bit-Output All-Digital Frequency Synthesizers With Forward and Feedback Spurs and Noise Cancellation

All-digital frequency synthesis architectures with phase and polar $\Sigma$ – $\Delta$ modulation feedback loops are introduced as a means to overcome the inherent spectral-quality limitations of forward-dithered all-digital frequency synthesizers represented by the family of pulse direct digital synthesizers. The spectrum of dithered pulse direct digital synthesizers is derived first, with and without modulation, as well as that of their variations with multiple dithered paths and with colored dithering resulting in lower noise level. The limited dynamic range achieved by forward-dithered all-digital frequency synthesizers motivates the introduction of phase and polar $\Sigma$ – $\Delta$ modulation feedback loop architectures which are modeled and analyzed to derive their noise transfer functions. Extensive MATLAB simulation illustrates the suppressed near-in noise and the high spurs-free dynamic range the two $\Sigma$ – $\Delta$ schemes can achieve and the wideband spurs-free output of the polar one. Detailed analysis and implementation aspects of the techniques are outside the scope of the paper.

Application and Debugging of All-Digital Frequency Synthesizer

Presents the working principle of Integrated PLL chip Si4133, this paper presents the implementation of a 375MHz local oscillator for a super heterodyne transmitter/receiver by using Si4133.Using programming method to set the divider register Internal chip. In addition, this paper discuss the methods for decreases the phase noise. Debugging circuit using ICCAVR software , and show the debugging results. Facts show that the phase noise and spurious of the frequency synthesizer is low, and it is practical.

Development of low‐complexity all‐digital frequency locked loop as 500 MHz reference clock generator for field‐programmable gate array

The authors report the development of an on-chip 500 MHz reference clock generator as a part of a clock manager for a field-programmable gate array. The generator is implemented in the form of an all-digital frequency locked loop (ADFLL) in architecture of low complexity and high modularity. For the development of the ADFLL, they propose a new circuit that employs two under-sampled 1-bit ΔΣ frequency-to-digital converters to convert a frequency difference into a proportional distributed pulsewidth. By the combination of the proposed circuit with a conventional phase-and-frequency detector, a frequency comparator is implemented and can indicate its two input frequency conditions, that is, (i) equal to, (ii) lower than or (iii) higher than. The ADFLL which adopts the proposed frequency comparator is implemented in a 90 nm CMOS technology. Consuming 2.64 mW from a 1.2 V supply, the ADFLL shows about 50 µs of locking time at the frequency accuracy of 99.2% while operating at 500 MHz and being driven by a 10 MHz reference clock.

Single-Bit Digital Frequency Synthesis via Dithered Nyquist-Rate Sinewave Quantization

Single-Bit Nyquist-rate quantization of sinewaves with random dithering is studied as a means for all-digital frequency synthesis. Quantizer's output spectrum is analytically derived and related to the cumulative distribution function of the random dither formed by independent and identically distributed random variables. Necessary and sufficient conditions for spurs-free output are derived. The noise floor level due to random dithering is derived analytically and the output dynamic range is defined. The trade-off between selective frequency-spurs presence and dynamic range improvement is studied. Several MATLAB examples illustrate the theory and its applications.

THE DESIGN AND IMPLEMENTATION OF A WIRELESS DATA ACQUISITION/TRANSMITTING SYSTEM FOR EURO-BALISE

This paper presents a design and implementation of a wireless data acquisition/transmitting system for Euro-balise. The presented system contains three parts: a power signal generator, a receiver and a transmitter. We also propose an all-digital coherent-like frequency shift keying (FSK) demodulator for the receiver of the system. The proposed demodulator based on the use of multi-bit XOR gates and a mean value filter can improve bit error ratio (BER) performance without increasing obvious complexity. Differential bi-phase level (DBPL) coding is adopted to ensure the reliability of the transmitter. The FSK demodulator and DBPL coder was implemented on field programmable gate array (FPGA). Hardware test results show that the equipment based on the presented system has good application in reading and writing data of the Euro-balise.

주파수 판별기 구조 및 잡음 성능 분석

주파수 판별기는 주파수를 디지털 비트 신호로 변환해주는 회로로서 변조기, 동기화 회로 등에 쓰인다. 본 논문에서는 여러 종류의 일차, 이차 주파수 판별기의 구조를 모델링하고 양자화 잡음 성능을 분석하며, 새로운 구조의 델타-시그마 주파수 판별기 구조를 제안한다. 이론적 분석과 유도된 수식으로부터 출구 잡음을 구하고 모의실험으로 타당성을 검증하였다. 제안된 주파수 판별기는 전 디지털 회로로서 전 디지털 위상 잠금 루프의 궤환 경로에 적용될 수 있다. Frequency detector is a circuit that converts the frequency to a digital representation and finds its application in various fields such as modulator and synchronization circuitry. In this paper, a couple of first-order and second-order frequency discriminator structures are modeled and analyzed with their quantization noise sources. Also a delta-sigma frequency detector architecture is proposed. Through theoretical analysis and derived equations, the output noise is obtained, which is validated by simulation. The proposed all-digital frequency discriminator may be applied in the feedback path of the all-digital phase-locked loop.

An All-Digital PLL Frequency Synthesizer With an Improved Phase Digitization Approach and an Optimized Frequency Calibration Technique

This paper presents an all-digital phase-locked loop (ADPLL) that features separate use of integer and fractional parts for the phase digitization in the feedback path. This separation simplifies the circuit implementation allowing reduced power consumption and silicon area. The proposed arrangement frees the ADPLL from potential metastability hazard during fine-tuning operation. Furthermore, it eliminates spurious tones associated with frequency reference retiming. In addition, the ADPLL employs an original frequency calibration technique that allows an extremely fine calibration resolution with minimized calibration time. Theoretical analysis is provided for both the architectural modification and frequency calibration technique. The ADPLL has been implemented in a 65-nm CMOS. Its simulation and measurement results are presented.

A Dither-Less All Digital PLL for Cellular Transmitters

An all-digital frequency synthesizer for cellular transmitter is presented. Low phase-noise is achieved both in-band and out-of-band exploiting a 2-dimensional Vernier time-to-digital converter and a dither-less digitally controlled oscillator. These building blocks heavily rely on digital calibration techniques to precisely and efficiently implement two-point modulation and spur cancellation in the presence of implementation impairments. The presented prototype shows an in-band phase noise of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${-}$</tex> </formula> 108 dBc/Hz, an out-of-band phase noise of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${-}$</tex></formula> 160 dBc/Hz @20 MHz and in-band fractional spurs below <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${-}$</tex> </formula> 50 dBc. These results are obtained for an output carrier of 1.8 GHz, a reference clock of 26 MHz, with a power consumption of 41.6 mW.

Direct All-Digital Frequency Synthesis Techniques, Spurs Suppression, and Deterministic Jitter Correction

Direct all-digital frequency synthesizers are favored by modern nanoscale CMOS technologies but suffer from strong frequency spurs and timing irregularities. To counter these drawbacks various jitter-correction and spurs-suppression techniques have been proposed. This paper presents a comprehensive literature review and a comparative study of such techniques, applied to popular direct all-digital frequency synthesis cores, identifying their strengths and weaknesses.