All-digital Frequency Synthesizer Research Articles

A VLSI Digital Circuit Platform for Performing Deterministic Stochastic Computing in the Time Dimension Using Fraction Operations on Rational Numbers

Stochastic computing (SC) is a method of expressing values in streams of random bits and performing computation with bitwise operations on the streams. Recently, it was found that SC can be conducted on deterministic bitstreams where a numerical value is represented uniformly by sections of 1s and 0s. This leads to deterministic SC, where the computing result can be 100% accurate. However, at the current stage, its circuit implementation has not reached the level of practicality. Moreover, the expressible values for operands are theoretically limited. An all-digital frequency synthesizer, time-average-frequency direct period synthesis (TAF-DPS), is proposed here as a hardware platform for performing deterministic SC in the time dimension. The TAF-DPS is used as a rational-number-to-time converter (RNTC), transforming a rational number into an electrical waveform. Waveforms of unique frequencies and duty cycles are then generated according to the operand values. Instead of digital bitwise operations, each computation is carried out in the time regime on waveforms. Hence, it can be regarded as an “analog-like” logical operation. This RNTC-based time-domain operation opens up a subfield of SC: rational number stochastic computing (RN-SC). In RN-SC, fraction computation can be executed with logic gates, and the result is 100% accurate. The enabling factor is the improvement in resource utilization since the time dimension is exploited more efficiently. With this extra resource of time, expansion of the scope of SC is expected. In this article, the working principle is elucidated, and the circuit is discussed. Furthermore, a field-programmable gate array (FPGA) prototype is created to validate this platform for SC. The aim of this work is to create a practical tool for broadening the use of SC.

Chip Design of an All-Digital Frequency Synthesizer with Reference Spur Reduction Technique for Radar Sensing

5.2-GHz all-digital frequency synthesizer implemented proposed reference spur reducing with the tsmc 0.18 µm CMOS technology is proposed. It can be used for radar equipped applications and radar-communication control. It provides one ration frequency ranged from 4.68 GHz to 5.36 GHz for the local oscillator in RF frontend circuits. Adopting a phase detector that only delivers phase error raw data when phase error is investigated and reduces the updating frequency for DCO handling code achieves a decreased reference spur. Since an all-digital phase-locked loop is designed, the prototype not only optimized the chip dimensions, but also precludes the influence of process shrinks and has the advantage of noise immunity. The elements of novelties of this article are low phase noise and low power consumption. With 1.8 V supply voltage and locking at 5.22 GHz, measured results find that the output signal power is −8.03 dBm, the phase noise is −110.74 dBc/Hz at 1 MHz offset frequency and the power dissipation is 16.2 mW, while the die dimensions are 0.901 × 0.935 mm2.

A 0.9–5.8-GHz Software-Defined Receiver RF Front-End With Transformer-Based Current-Gain Boosting and Harmonic Rejection Calibration

A 0.9–5.8-GHz receiver RF front-end (RFE) integrating a dual-band low-noise transconductance amplifier (LNTA), a passive harmonic-rejection (HR) down-conversion mixer, and an all-digital frequency synthesizer for software-defined radios are presented. A switchable three-coil transformer acting as the interface between the LNTA and the mixer features current-gain boosting in addition to wideband operation. Automatic local oscillator phase-error detection and calibration circuitry is implemented for the mixers to achieve high HR ratio (HRR). Fabricated in 65-nm CMOS, the RFE measures the noise figure between 2.9 and 3.8 dB, the third-order input intercept point (IIP3) between −1.6 and −12.8 dBm, the third-order HRR of 81 dB, and the fifth-order HRR of 70 dB, while consuming 66–82 mA from a 1.2-V supply and occupying a chip area of 4.2 mm2.

Increasing a Resolution of Time to Digital Converter

Time to digital converter (TDC) is one of the main blocks of all-digital frequency synthesizer (FS), where it is used as phase detector. The output of TDC is digital, therefore it introduces quantization noise to the output of FS. The resolution of TDC has to be increased, to improve phase noise level at the output of FS. It can be achieved by improving CMOS technology or structure of the TDC. The simplest TDC is based on inverter delay line. Its resolution is inversely proportional to the time interval, which can be measured with such TDC, i.e. delay time of the inverter. Decreasing of this delay is essence of technological increasing of TDC’s resolution. In this work the dependency of inverter delay on technological parameters is shown and its value is calculated in 65 nm CMOS technology. Calculations show, that in this technology delay time of the inverter can vary from 7 ps to 54 ps. If the design is restricted to the usage of specific CMOS technology, in which inverter’s delay does not ensure needed noise level at the output of FS, structure of the TDC needs to be improved. The aim of this improvement is to measure time interval smaller than inverter’s delay. Some of the TDC structures, which can measure sub-inverter delay time, are reviewed in this work: TDC – Vernier delay line, TDC – 2D Vernier plane, stochastic, ring and multistage TDCs.

Single-Bit All-Digital Frequency Synthesis Using Homodyne Sigma-Delta Modulation.

All-digital frequency synthesis using bandpass sigma-delta modulation to achieve spectrally clean single-bit output is presented and mathematically analyzed resulting in a complete model to predict the stability and output spectrum. The quadrature homodyne filter architecture is introduced resulting in efficient implementations of carrier-frequency-centered bandpass filters for the modulator. A multiplierless version of the quadrature homodyne filter architecture is also introduced to reduce complexity while maintaining a clean in-band spectrum. MATLAB and SIMULINK simulation results present the potential capabilities of the synthesizer architectures and validate the accuracy of the developed theoretical framework.

Spurs-Free Single-Bit-Output All-Digital Frequency Synthesizers With Forward and Feedback Spurs and Noise Cancellation

All-digital frequency synthesis architectures with phase and polar $\Sigma$ – $\Delta$ modulation feedback loops are introduced as a means to overcome the inherent spectral-quality limitations of forward-dithered all-digital frequency synthesizers represented by the family of pulse direct digital synthesizers. The spectrum of dithered pulse direct digital synthesizers is derived first, with and without modulation, as well as that of their variations with multiple dithered paths and with colored dithering resulting in lower noise level. The limited dynamic range achieved by forward-dithered all-digital frequency synthesizers motivates the introduction of phase and polar $\Sigma$ – $\Delta$ modulation feedback loop architectures which are modeled and analyzed to derive their noise transfer functions. Extensive MATLAB simulation illustrates the suppressed near-in noise and the high spurs-free dynamic range the two $\Sigma$ – $\Delta$ schemes can achieve and the wideband spurs-free output of the polar one. Detailed analysis and implementation aspects of the techniques are outside the scope of the paper.

Application and Debugging of All-Digital Frequency Synthesizer

Presents the working principle of Integrated PLL chip Si4133, this paper presents the implementation of a 375MHz local oscillator for a super heterodyne transmitter/receiver by using Si4133.Using programming method to set the divider register Internal chip. In addition, this paper discuss the methods for decreases the phase noise. Debugging circuit using ICCAVR software , and show the debugging results. Facts show that the phase noise and spurious of the frequency synthesizer is low, and it is practical.

Single-Bit Digital Frequency Synthesis via Dithered Nyquist-Rate Sinewave Quantization

Single-Bit Nyquist-rate quantization of sinewaves with random dithering is studied as a means for all-digital frequency synthesis. Quantizer's output spectrum is analytically derived and related to the cumulative distribution function of the random dither formed by independent and identically distributed random variables. Necessary and sufficient conditions for spurs-free output are derived. The noise floor level due to random dithering is derived analytically and the output dynamic range is defined. The trade-off between selective frequency-spurs presence and dynamic range improvement is studied. Several MATLAB examples illustrate the theory and its applications.

A High Resolution First Order Noise-Shaping Vernier Time-to-Digital Converter

In this paper, we propose a noise reduction method for a Vernier Time-to-Digital Converter (VTDC) using a first-order noise shaping structure and a gated ring oscillator (GRO). An 11bit VTDC with 4 p s effective resolution was designed and developed for a high performance All Digital Frequency Synthesizer (ADFS). The VTDC realized in 180nm CMOS, its power consumption depending on the time difference between input edges; 1 to 11mA from a 1.5 V supply.

An All-Digital PLL Frequency Synthesizer With an Improved Phase Digitization Approach and an Optimized Frequency Calibration Technique

This paper presents an all-digital phase-locked loop (ADPLL) that features separate use of integer and fractional parts for the phase digitization in the feedback path. This separation simplifies the circuit implementation allowing reduced power consumption and silicon area. The proposed arrangement frees the ADPLL from potential metastability hazard during fine-tuning operation. Furthermore, it eliminates spurious tones associated with frequency reference retiming. In addition, the ADPLL employs an original frequency calibration technique that allows an extremely fine calibration resolution with minimized calibration time. Theoretical analysis is provided for both the architectural modification and frequency calibration technique. The ADPLL has been implemented in a 65-nm CMOS. Its simulation and measurement results are presented.

A Dither-Less All Digital PLL for Cellular Transmitters

An all-digital frequency synthesizer for cellular transmitter is presented. Low phase-noise is achieved both in-band and out-of-band exploiting a 2-dimensional Vernier time-to-digital converter and a dither-less digitally controlled oscillator. These building blocks heavily rely on digital calibration techniques to precisely and efficiently implement two-point modulation and spur cancellation in the presence of implementation impairments. The presented prototype shows an in-band phase noise of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${-}$</tex> </formula> 108 dBc/Hz, an out-of-band phase noise of <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${-}$</tex></formula> 160 dBc/Hz @20 MHz and in-band fractional spurs below <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${-}$</tex> </formula> 50 dBc. These results are obtained for an output carrier of 1.8 GHz, a reference clock of 26 MHz, with a power consumption of 41.6 mW.

Direct All-Digital Frequency Synthesis Techniques, Spurs Suppression, and Deterministic Jitter Correction

Direct all-digital frequency synthesizers are favored by modern nanoscale CMOS technologies but suffer from strong frequency spurs and timing irregularities. To counter these drawbacks various jitter-correction and spurs-suppression techniques have been proposed. This paper presents a comprehensive literature review and a comparative study of such techniques, applied to popular direct all-digital frequency synthesis cores, identifying their strengths and weaknesses.

State-of-the-Art and Future Directions of High-Performance All-Digital Frequency Synthesis in Nanometer CMOS

The past several years have successfully brought all-digital techniques to the RF frequency synthesis, which could arguably be considered one of the last strong bastions of the traditionally-analog design approaches. With their high sensitivity and high dynamic range requirements, the RF circuits have long had a good excuse to avoid any possible source of digital switching activity. With the constant scaling of CMOS feature size and the merciless push for integration, the existence of almost free and powerful digital logic could not go unnoticed. Hence, the environment was ripe to transform the RF functions into digital realizations, as well as to apply digital assistance to help with the performance of RF circuits. This paper revisits the digitization journey of the traditional charge-pump PLL that has resulted in an all-digital frequency synthesizer with the best-in-class RF performance while occupying only a fraction of the silicon area and consuming a fraction of the power. The paper also offers a few novel techniques to further improve area, current consumption, testability, and reliability of frequency synthesizers.

All-Digital Frequency Synthesizer Using a Flying Adder

This brief presents an all-digital frequency synthesizer based on the flying adder (FA) architecture. The FA is a fascinating architecture for frequency synthesizer designs due to its simplicity and effectiveness. The FA-based frequency synthesizer can simply use a set of multiple phase reference signals to generate a desired frequency to achieve fast frequency switching. In the proposed work, the frequency synthesizer adopts an all-digital phase-locked loop to provide a steady reference signal for the FA. The proposed frequency synthesizer is implemented in a standard 0.18-μm CMOS cell-based technology, and the core area is 0.16 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The output frequency range is 39.38-226 MHz, and the peak-to-peak jitter is less than 130 ps.

A Quadrature Modulation Transmitter Using Two Frequency Synthesizers

This brief analyzes a novel quadrature modulation transmitter architecture. The proposed architecture consists of only two frequency synthesizers, thereby reducing the RF and analog components such as RF mixer, analog filter, and digital-to-analog converter. Simulation results show that the bit-error rate and the spectral efficiency of the proposed method are close to those of conventional quadrature modulation scheme. The quadrature modulation transmitter can be implemented fully digitally through the proposed architecture if the all-digital frequency synthesizer is used.