Aid Of Simulation Tools Research Articles

Fault-tolerant strategies in MMC-based high power magnet supply for particle accelerator

Many particle accelerators require to supply chains of magnets with high quality, high magnitude, cycling currents. To do this, the power converters need to provide high output voltages, reaching in some cases tens of kilovolts. Additionally, converters are required to store the magnet energy during de-magnetization cycles. For such application, Full-bridge Modular Multilevel Converters (FB-MMC) could be used given their capacity to store energy and their inherent reliability. In this sense, one of the most interesting features of the proposed topology is the possibility of bypassing one or several submodules in the event of a fault or malfunction. By doing this, it is possible to ride-through the failure of a component and avoid the interruption of the accelerator operation.However, when the number of submodules is small, this operation could lead to an excessive charge of the healthy cells, increasing the risk of secondary failures. Besides, undesired harmonic content could appear on the output current, degrading the operation of the accelerator. It is then necessary to implement strategies that allow to remove a faulty cell without significantly impacting the operation of the remaining ones and of the converter itself.Accordingly, the purpose of this article is to investigate several of these strategies and assess them. By means of detailed computer simulations, the behaviour of the converter during normal and submodule fault conditions is analysed. Then, several fault-tolerant strategies are described, verified and compared with the aid of simulation tools. The results show the effectiveness of the analysed strategies in avoiding the overvoltage on the healthy submodules after a cell bypass and the little impact of this operation on the quality of the converter output current.

Welding of girders with thick plates — Fabrication, measurement and simulation

This article presents experimental and numerical results of the fabrication of welded plate girders under workshop conditions. Main concerns are the prediction of imperfections with the aid of simulation tools and/or simplified engineering models. Their impact on the component design is evaluated in a case study. Special focus is put on the effect of residual welding stress. For this, different simplified distributions are compared with results from welding simulation. The findings confirm the thesis that present recommendations on the implementation of weld-induced imperfections must be rated conservative. This suggests that it is necessary to establish new models. Guidance on future problems in this context will be given.

Conceptual analysis of single-feed heterogeneous distillation columns

<p class="Abstractandkeywordscontent">Separation in heterogeneous distillation columns is attained by interaction of two liquid and one vapor phases, interaction of three phases involves complexities due to the determination of vapor-liquid-liquid equilibrium and hence, in the design of separation units. Nevertheless, the liquid-liquid equilibrium allows developing separations that may be unfeasible by vapor-liquid equilibrium. In this way, heterogeneous azeotropic distillation is a useful operation for the separation of azeotropic and close-boiling mixtures. In this work, a new methodology for evaluating the feasibility of this process is developed. This methodology is an extension of that proposed by Castillo <em>et al</em>. (1998) for homogeneous systems. Operation leaves for heterogeneous systems are calculated using the concept of pinch point curves in order to establish the process feasibility. Heterogeneous columns with external decanter are considered as the only heterogeneous stage (OHED: only heterogeneous external decanter). The initialization process for the column calculation requires the selection of the distillate composition using thermodynamic criteria in order to guarantee homogeneous phases within the column. A system with industrial and academic relevance was considered as case study: water-acetic acid-amyl acetate. Results show that the developed shortcut method allows evaluating process feasibility and estimating design parameters, without the use of trial and error procedures implemented, with the aid of simulation tools.</p><div> </div>

Modelling, Performance Analysis and Design of WPAN Systems

This paper covers the main issues that must be solved in order to design and analyse the performance of Wireless Personal Area Networks (WPANs) with the aid of simulation tools. We review state-of-the-art channel models to account for small- and large-scale propagation conditions in waveform- and system-level simulations. When dealing with waveform simulations, we also look at Montecarlo and importance sampling techniques that allow efficient estimation of error probabilities. Additionally, discrete channel models are introduced to efficiently link both waveform- and system-level approaches and we point out some methods to obtain the model parameters that are suitable for the wireless environment. The discussion of these techniques is complemented with two application examples that show the use of the different simulation levels for system design and performance study. With the paradigm of Bluetooth piconets we illustrate the usefulness of discrete channel models and we consider the design of an OFDM-based WPAN system to exemplify simulation from a waveform-level point of view.

An integrated CAD system for algorithm-specific IC design

LAGER is an integrated computer-aided design system for algorithm-specific integrated circuit design, targeted at applications such as speech processing, image processing, telecommunications, and robot control. LAGER provides user interfaces at behavioral, structural, and physical levels and allows easy integration of novel CAD tools. LAGER consists of a behavioral mapper and a silicon assembler. The behavioral mapper maps the behavior onto a parameterized structure to produce microcode and parameter values. The silicon assembler then translates the filled-out structural description into a physical layout, and, with the aid of simulation tools, the user can fine tune the data path by iterating this process. The silicon assembler can also be used without the behavioral mapper for high-sample-rate applications. A number of algorithm-specific ICs designed with LAGER have been fabricated and tested, and as examples, a robot arm controller chip and a real-time image segmentation chip are described.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>