Aggressor Nets Research Articles

Modeling and Analytical Studies of an Ink-Jet Printed Sensing Framework for Measuring Sub-Soil Nitrate

We have demonstrated ink-jet printed IoT sensor sheets capable of quantifying long-term soil nitrate concentration as shown in Fig. 1a. However, our previous data indicates that long routing lines contribute to lossy signals, noise, and electrode cross-talk within the sensor sheet. Using this current version of the sensor sheets leads to following challenges: 1) unbalanced sensing performance at different locations. Sensors further away from the power source report over 45% signal loss and large sensing current variation due to the unbalanced signal routing as seen in Fig. 1b. 2) Noisy sensing incurred by the signal crosstalk. As Fig.1c shows, the interference from neighboring sensors can largely deviate the sensing of a target sensor. 3) Inaccurate sub-soil nitrate analysis because of imperfect sensing results from failed or noisy sensors. This paper focuses on the development of mathematical models to quantify the sensing crosstalk among targeted sensors and other idle sensors for high-accurate sensing, and use the models as guides for robust VLSI sensor array design and routing architecture. A unique aspect of our approach is to use sensor cross-talk as a technique to identify sensor failures. The simple linear and nonlinear models, as well as advanced 2pi model used to measure the coupling between victim and aggressor nets in VLSI physical design, will be implemented on the ink-jet printed sensor sheets. Figure 1

Feasible Aggressor-Set Identification Under Constraints for Maximum Coupling Noise

In this paper, we consider the problem of identifying a feasible set of aggressor nets that would induce maximum crosstalk noise or delay pushout on a coupled victim net, under given logical constraints. We present a novel mathematical formulation of this problem and propose a Lagrangian relaxation-based approach for solving it efficiently and optimally. Experimental results show that the proposed approach is run-time efficient by a factor of up to 800 times in comparison to an exhaustive search approach and reduces timing pessimism by up to 36%. We also formulate and solve this problem while considering the noise susceptibility of the victim's receiving gate.

Accurate crosstalk noise modeling for early signal integrity analysis

In this paper, we propose an accurate and fast method to estimate the crosstalk noise in the presence of multiple aggressor nets for use in physical design automation tools. Since noise estimation is often part of the inner loop of optimization algorithms, very efficient closed-form solutions are needed. Previous approaches model aggressor nets one at a time, assuming that the coupling capacitance to all quiet aggressor nets are grounded. They also model the load from interconnect branches as a lumped capacitor, the value of which is the sum of interconnect and load capacitances of the branch. Finally, previous works typically use simple lumped 2-4-node circuit templates and employ a so-called dominant pole approximation to solve the template circuit. While these approximations allow for very fast analysis, they may result in significant underestimation of the noise. In this paper, we propose a new and more comprehensive fast noise estimation method. We propose a novel reduction technique for modeling quiet aggressor nets based on the concept of coupling point admittance. We also propose a reduction method to replace tree branches with effective capacitors which models the effect of resistive shielding. Furthermore, we model the simplified single aggressor net crosstalk noise problem using a 6-node template circuit and propose a new double pole approach to solve the template circuit. We have tested the proposed method on noise-prone interconnects from an industrial high-performance processor. Our results show a worst case error of 7.8% and an average error of 2.7%, while allowing for very fast analysis.

Driver modeling and alignment for worst-case delay noise

In this paper, we present a new approach to model the impact of cross-coupling noise on interconnect delay. We introduce a new linear driver model that accurately models the noise pulse induced on a switching signal net due to cross-coupling capacitance. The proposed model effectively captures the nonlinear behavior of the victim-driver gate during its transition and has an average error below 8% whereas the traditional approach using a Thevenin model incurs an average error of 48%. The proposed linear driver model enables the use of linear superposition which allows the analysis of large interconnects and an efficient determination of the worst-case transition times of the aggressor nets. We proposed a new approach to determine the worst-case alignment of the aggressor net transitions with respect to the victim net transition, emphasizing the need to maximize not merely the delay of the interconnect alone but the combined delay of the interconnect and receiver gate. We show that in the presence of multiple aggressor nets, the worst case delay may occur when their noise peaks are not aligned, although the error incurred from aligning all peaks is small in practice. We then show that the worst-case alignment time of the combined noise pulse from all aggressors with respect to the victim transition is a nonlinear function of the receiver gate output loading, the victim transition time, and the noise pulsewidth and height. To efficiently compute the worst-case alignment time, we propose a new representation of the alignment such that it closely fits a linear function of the input variables. The worst-case alignment time is then computed for a gate using a precharacterization approach, requiring only eight sample points while maintaining a small error. The proposed methods were implemented in an industrial noise analysis tool called ClariNet. Results on industrial designs, including a large PPCmicroprocessor design, are presented to demonstrate the effectiveness of our approach.

False-noise analysis using logic implications

Cross-coupled noise analysis has become a critical concern in today's VLSI designs. Typically, noise analysis makes the assumption that all aggressing nets can simultaneously switch in the same direction. This creates a worst- case noise pulse on the victim net that often leads to false noise violations. In this article we present a new approach that uses logic implications to identify the maximum set of aggressor nets that can inject noise simultaneously under the logic constraints of the circuit. We propose an approach to efficiently generate logic implications from a transistor-level description and propagate them in the circuit using ROBDD representations. We propose a new method for lateral propagation of implications and also show how tristate gates and high-impedance signal states can be handled using tristate implications. We then show that the problem of finding the worst-case logically feasible noise can be represented as a maximum weighted independent set problem and show how to efficiently solve it. Initially, we restrict our discussion to zero-delay implications, which are valid for glitch-free circuits, and then extend our approach to timed implications. The proposed approaches were implemented in an industrial noise analysis tool and results are shown for a number of industrial test cases. We demonstrate that a significant reduction in the number of noise failures can be obtained from considering the logic implications as proposed in this article, underscoring the need for false-noise analysis.