Aggressive Optical Proximity Correction Research Articles

Computational metrology and inspection (CMI) in mask inspection, metrology, review, and repair

Abstract Mask manufacturers will be impacted by two significant technology requirements at 22 nm and below: the first is the more extensive use of resolution enhancement technologies (RET), such as aggressive optical proximity correction (OPC), inverse lithography technology (ILT), and source mask optimization (SMO); the second is the extreme ultraviolet (EUV) technology. Both will create difficulties for mask inspection, defect disposition, metrology, review, and repair. For example, the use of ILT and SMO significantly increases mask complexity, making mask defect disposition more challenging than ever. The EUV actinic inspection and AIMS™ will not be available for at least a few years, which make the EUV defect inspection and disposition more difficult, particularly regarding multilayer defects. Computational metrology and inspection (CMI), which has broad applications in mask inspection, metrology, review, and repair, has become essential to fill this technology gap. In this paper, several such CMI applications are presented and discussed.

Full-Chip Layout Optimization for Process Margin Enhancement Using Model-Based Hotspot Fixing System

As the design rule of integrated circuits is shrinking rapidly, it is necessary to use low-k1 lithography technologies. With low-k1 lithography, even if aggressive optical proximity correction is adopted, many sites become marginless spots, known as “hotspots”. For this problem, hotspot fixer (HSF) in design-for-manufacturability flow has been studied. In our previous work, we indicated the feasibility of layout modification using a simple line/space sizing rule for metal layers in 65-nm-node logic devices. However, in view of the continuous design-rule shrinkage and design complication, a more flexible modification method has become necessary to fix various types of hotspots. In this work, we have developed a brute-force model-based HSF. To further reduce the processing time, the hybrid flow of rule- and model-based HSFs is studied. The feasibility of such hybrid flow is studied by applying it to the full-chip layout modification of a logic test chip.

Study of the contour-based optical proximity correction methodology

As design rule continues to shrink, resolution enhancement techniques (RET) such as optical proximity correction (OPC) become more and more complex to enable design printability. As we know, typically integrated circuit (IC) layouts are simple shapes such as rectangles. However, high spatial frequency components of the mask spectrum that are not captured by the low-pass pupil result in a rounded image. In addition, the diffusion process in the postexposure bake (PEB) step makes the wafer rounding effects worse. This means that it is difficult to get the wafer image to match the design exactly at corners, even with the most aggressive OPC methodology. Therefore, pre-OPC site placement optimization is necessary to achieve high quality wafer images. In this work, a contour-based OPC methodology is proposed to minimize the time consumption in pre-OPC simulation site placement optimization and OPC job running. Rounded target contours that best describe the real intended wafer result are used as the target during OPC correction. By comparing classical OPC recipe-driven target point placement and contour-based OPC methodology, it is found that contour-based OPC methodology can achieve comparable image quality in a shorter turn around time (TAT) with fewer engineer resources.

Design freedom gets the brush-off [chip design

Various techniques have been used to push processes this far past the point where diffraction effects kick in. These have included using phase-shift masking to turn diffraction to the designers' advantage, and optical proximity correction (OPC) techniques, such as adding 'ears' to the corners of layout elements so that they are printed as right angles. The problem is that chipmakers are applying ever more Byzantine combinations of these techniques to keep up with shrinking process dimensions, and getting diminishing returns. Device characteristics are varying wildly as more aggressive OPC techniques are pressed into action. The chip equipment industry has been working to solve this for years, but couldn't persuade its customers that moving to 157nm illumination sources was worth the development costs given the marginal advantages it would bring over 193nm light. Unfortunately, the development of EUV lithography is fraught with difficulties. The solution to the 65 nm and 45 nm design for manufacture is new DFM routers. As they are DFM-aware they can run the rule-based checks and ensure that around 80 percent of the DFM problems are avoided. The layout team can then use model- based DFM to take care of the remaining 20 percent.

From 120 to 32 nm CMOS technology: development of OPC and RET to rescue optical lithography

Starting from the 120 nm CMOS technology node down to the 32 nm node, we have entered into a new lithographic regime. The wavelength has not changed (only 193 nm), and we move closer and closer to the theoretical optical resolution limit. Therefore, Resolution Enhancement Techniques (RET) have been developed in order to print all shapes properly and close the resolution gap. The primary RET developed are off-axis illumination, sub-resolution assist features and a phase shift mask. Moreover, working closer to the resolution limit implies bigger image distortion between the mask and the silicon. For this purpose OPC (Optical Proximity Correction) has been widely used by making mask pre-compensation of all non linear effects, optical diffraction and interference effects, resist and etch. RET and OPC are also fundamentally linked. RET such as off-axis illumination generates more distortion, and therefore justifies the need of more aggressive OPC, and RET techniques like Alt PSM and sub-resolution assist features are generated through the OPC infrastructure. From its first industrial utilization for 120 nm node to 32 nm prospectively, many evolutions have been seen for OPC. These include the generalisation to all lithographic layers, moving to pixel based simulation, usage of full chip simulation and verification, the incorporation of process window effects like Energy Latitude or Depth of Focus into the OPC algorithm, and inverse lithography approach. For RET, we have seen huge differentiation depending on the type of application, such as logic or memory. In conclusion, we need to consider design as a third party that is playing a key role in this RET–OPC synergy. To use more aggressive RET and reduce the cycle time of OPC recipe development, more regular designs are considered as a key enabler for the future: they will allow logic makers to consider RET options that are pushed as far as those used by memory makers. To cite this article: Y. Trouiller, C. R. Physique 7 (2006).