AES S-box Research Articles

Chaos Meets Cryptography: Developing an S-Box Design with the Rössler Attractor

The volume of data transmitted over networks has significantly increased in recent years. For that reason, safeguarding the privacy, authenticity, and confidentiality of specific data is imperative, necessitating a type of encryption; symmetric encryption, known for its computational efficiency, is ideal for securing extensive datasets. A principal component within symmetric key algorithms is the substitution box (S-box), which creates confusion between plaintext and ciphertext, enhancing the security of the process. This paper proposes a fashion method to create chaotic S-boxes using the Rössler attractor as a chaotic process and the Rijndael S-box as a permutation box. The proposed S-boxes are evaluated with bijectivity, non-linearity (NL), strict avalanche criterion (SAC), bit independence criterion (BIC), linear approximation probability (LAP), and differential uniformity (DU). The analyses show that the proposed method helps generate a high-resistance S-box to well-known attacks and high efficiency, executing in short computational time.

Batch generating keyed strong S-Boxes with high nonlinearity using 2D hyper chaotic map

Cryptanalysis result of the S-Box construction in AES revealed that, (1) the number of irreducible polynomials can be extend to 30, (2) if we ignore the existence of fixed point(s) and reverse fixed point(s) in an S-Box, the affine transformation constant c can select from [01, FF], and (3) the S-Box in AES is fixed, which causes potential security risks to the AES algorithm. Based on the above analysis, first we constructed a non-degenerate 2D enhanced quadratic map (2D-EQM) with ergodicity and randomness, and then used it to generate affine transformation matrices and affine transformation constants which were applied to seed S-Boxes to generate a batch of keyed strong S-Boxes with high nonlinearity. Furthermore, we counted that of all the generated 4.0913 × 1022 S-Boxes, about 5.4414 × 1020 of them can still keep the nonlinearity of 112. Finally, we used six criteria to evaluate the performance of constructed S-Boxes. Security and statistical analysis demonstrated the effectiveness and practicability of the proposed S-Box batch generating algorithm.

Hardware Implementation of High-Throughput S-Box in AES for Information Security

Hardware Implementation of High-Throughput S-Box in AES for Information Security

SPSA: Semi-Permanent Stuck-At fault analysis of AES Rijndael SBox

SPSA: Semi-Permanent Stuck-At fault analysis of AES Rijndael SBox

A Lightweight Image Encryption Algorithm Based on Chaotic Map and Random Substitution.

Chaotic-maps-based image encryption methods have been a topic of research interest for a decade. However, most of the proposed methods suffer from slow encryption time or compromise on the security of the encryption to achieve faster encryption. This paper proposes a lightweight, secure, and efficient image encryption algorithm based on logistic map, permutations, and AES S-box. In the proposed algorithm, SHA-2 based on the plaintext image, a pre-shared key, and an initialization vector (IV) are used to generate the initial parameters for the logistic map. The logistic map chaotically generates random numbers, which are then used for the permutations and substitutions. The security, quality, and efficiency of the proposed algorithm are tested and analyzed using a number of metrics, such as correlation coefficient, chi-square, entropy, mean square error, mean absolute error, peak signal-to-noise ratio, maximum deviation, irregular deviation, deviation from uniform histogram, number of pixel change rate, unified average changing intensity, resistance to noise and data loss attacks, homogeneity, contrast, energy, and key space and key sensitivity analysis. Experimental results reveal that the proposed algorithm is up to 15.33× faster compared to other contemporary encryption methods.

MODIFICATION ADVANCED ENCRYPTION STANDARD (AES) ALGORITHM WITH PERFECT STRICT AVALANCHE CRITERION S-BOX

The Advanced Encryption Standard or better known as the AES Algorithm is a standard algorithm and has been widely used as an application of cryptography. Currently, a lot of research is developing about attacks on the AES algorithm. Therefore, there have been many studies related to modifications to the AES algorithm with the aim of increasing the security of the algorithm and to produce alternatives to encryption algorithms that can be used to secure data. In this study, modifications were made to the AES algorithm by replacing the S-box using the perfect SAC S-box in the SubBytes process. The Perfect SAC S-box has an exact SAC average value of 0.5. The S-box that will be used must have good security strength, therefore the perfect SAC S-box is tested, namely the AC, SAC, BIC, XOR Table Distribution, and LAT Distribution tests. Based on the results of the study, it was found that the perfect SAC S-box had almost the same S-box test results as the AES S-box. Furthermore, after the perfect SAC S-box is applied to the AES algorithm, it is analyzed how the effect of these modifications on the AES algorithm uses randomness testing for the block cipher algorithm, namely the strict avalanche criterion (SAC) test. The results of the AES test with perfect SAC S-box can meet the SAC test since the second round with better results than the original AES algorithm with SAC values of 0.5003 and 0.5019.

Low delay AES S-box designs based on matrix merging method

Low delay AES S-box designs based on matrix merging method

Proving SIFA protection of masked redundant circuits

Implementation attacks like side-channel and fault attacks pose a considerable threat to cryptographic devices that are physically accessible by an attacker. As a consequence, devices like smart cards implement corresponding countermeasures like redundant computation and masking. Recently, statistical ineffective fault attacks (SIFA) have been shown to be able to circumvent these classical countermeasure techniques. We present a new approach for verifying the SIFA protection of arbitrary masked implementations in both hardware and software. The proposed method uses Boolean dependency analysis, factorization, and known properties of masked computations to show whether the fault detection mechanism of redundant masked circuits can leak information about the processed secret values. We implemented this new method in a tool called Danira, which can show the SIFA resistance of cryptographic implementations like AES S-Boxes within minutes.

Enhancing the Performance of the Advanced Encryption Standard (AES) Algorithm Using Multiple Substitution Boxes

This paper proposes for a modified version of the AES algorithm using multiple substitution boxes (S-Boxes). While many studies have been conducted specifically on modifying the S-Box, these studies were made to replace the Rijndael S-boxes in the AES cipher. We propose to implement two substitution boxes, where the first S-Box is the Rijndael S-box and will be used as is. The second S-Box was constructed through an XOR operation and affine transformation and will replace the MixColumns operation within the internal rounds in the cipher. Based on simulation testing conducted, it was found out that there is a significant difference in the speed performance between the two versions favouring the proposed AES algorithm using multiple S-Box. The findings also revealed that in both encryption and decryption processes, the AES-2SBox performed more efficiently at 27.638% and 108.369% respectively as compared to the original AES algorithm. However, when tested using the avalanche effect, the changes in the output bits were below the minimum expected rate.

Higher-Order Lookup Table Masking in Essentially Constant Memory

Masking using randomised lookup tables is a popular countermeasure for side-channel attacks, particularly at small masking orders. An advantage of this class of countermeasures for masking S-boxes compared to ISW-based masking is that it supports pre-processing and thus significantly reducing the amount of computation to be done after the unmasked inputs are available. Indeed, the “online” computation can be as fast as just a table lookup. But the size of the randomised lookup table increases linearly with the masking order, and hence the RAM memory required to store pre-processed tables becomes infeasible for higher masking orders. Hence demonstrating the feasibility of full pre-processing of higher-order lookup table-based masking schemes on resource-constrained devices has remained an open problem.
 In this work, we solve the above problem by implementing a higher-order lookup table-based scheme using an amount of RAM memory that is essentially independent of the masking order. More concretely, we reduce the amount of RAM memory needed for the table-based scheme of Coron et al. (TCHES 2018) approximately by a factor equal to the number of shares. Our technique is based upon the use of pseudorandom number generator (PRG) to minimise the randomness complexity of ISW-based masking schemes proposed by Ishai et al. (ICALP 2013) and Coron et al. (Eurocrypt 2020). Hence we show that for lookup table-based masking schemes, the use of a PRG not only reduces the randomness complexity (now logarithmic in the size of the S-box) but also the memory complexity, and without any significant increase in the overall running time. We have implemented in software the higher-order table-based masking scheme of Coron et al. (TCHES 2018) at tenth order with full pre-processing of a single execution of all the AES S-boxes on a ARM Cortex-M4 device that has 256 KB RAM memory. Our technique requires only 41.2 KB of RAM memory, whereas the original scheme would have needed 440 KB. Moreover, our 8-bit implementation results demonstrate that the online execution time of our variant is about 1.5 times faster compared to the 8-bit bitsliced masked implementation of AES-128.

Deep K-TSVM: A Novel Profiled Power Side-Channel Attack on AES-128

The appearance of deep neural networks for Side-Channel leads to strong power analysis techniques for detecting secret information of physical cryptography implementations. Generally, deep learning techniques do not suffer the difficulties of template attacks such as trace misalignment. However, the generalization of a trained deep neural network that can accurately predict Side-Channel leakages largely depends on its adjustable variables (parameters of a neural network). Although pre-training is no longer mandatory, it is needed for parameter selection of a deep neural network to improve the success rate and provide a better insight into the network’s inner functionality. In this paper, we propose a novel model via Twin support vector with a deep kernel approach when targeting a hardware implementation of AES-128. The proposed model is pre-trained with the Restricted Boltzmann Machine method in a layer-wise manner and then fine-tuned via gradient descent. Further, we used the grid search technique for the selection of each hyperparameter which is used to compute class probabilities of every test trace in our deep model based side-channel attack. Based on our analysis and experiments, this model empirically shows its effectiveness by outperforming some of its competitors in profiling attack methods such as convolutional neural networks and multilayer perceptron models. We also evaluate our model on both masked and unmasked AES implementation. The results indicate that the proposed approach has achieved a success rate of greater than 99% even with a single trace using Keras library with Tensorflow. We investigate the correct “key rank” according to the number of traces; our model reaches the key $ rank\leq 10 $ when attacking the third AES SBox.

Cryptographic strength evaluation of AES s-box variants

Cryptographic strength evaluation of AES s-box variants

Neural Network-based Inherently Fault-tolerant Hardware Cryptographic Primitives without Explicit Redundancy Checks

Fault injection-based cryptanalysis is one of the most powerful practical threats to modern cryptographic primitives. Popular countermeasures to such fault-based attacks generally use some form of redundant computation to detect and react/correct the injected faults. However, such countermeasures are shown to be vulnerable to selective fault injections. In this article, we aim to develop a cryptographic primitive that is fault tolerant by its construction and does not require to compute the same value multiple times. We utilize the effectiveness of Neural Networks (NNs), which show “some degree” of robustness by functioning correctly even after the occurrence of faults in any of its parameters. We also propose a novel strategy that enhances the fault tolerance of the implementation to “high degree” (close to 100%) by incorporating selective constraints in the NN parameters during the training phase. We evaluated the performance of revised NN considering both software and FPGA implementations for standard cryptographic primitives like 8×8 AES SBox and 4×4 PRESENT SBox. The results show that the fault tolerance of such implementations can be significantly increased with the proposed methodology. Such NN-based cryptographic primitives will provide inherent resistance against fault injections without requiring any redundancy countermeasures.

Hardware Performance Evaluation of Authenticated Encryption SAEAES with Threshold Implementation

SAEAES is the authenticated encryption algorithm instantiated by combining the SAEB mode of operation with AES, and a candidate of the NIST’s lightweight cryptography competition. Using AES gives the advantage of backward compatibility with the existing accelerators and coprocessors that the industry has invested in so far. Still, the newer lightweight block cipher (e.g., GIFT) outperforms AES in compact implementation, especially with the side-channel attack countermeasure such as threshold implementation. This paper aims to implement the first threshold implementation of SAEAES and evaluate the cost we are trading with the backward compatibility. We design a new circuit architecture using the column-oriented serialization based on the recent 3-share and uniform threshold implementation (TI) of the AES S-box based on the generalized changing of the guards. Our design uses 18,288 GE with AES’s occupation reaching 97% of the total area. Meanwhile, the circuit area is roughly three times the conventional SAEB-GIFT implementation (6229 GE) because of a large memory size needed for the AES’s non-linear key schedule and the extended states for satisfying uniformity in TI.

Protecting against Statistical Ineffective Fault Attacks

Statistical Ineffective Fault Attacks (SIFA) pose a threat for many practical implementations of symmetric primitives. Countermeasures against both power analysis and fault attacks typically do not prevent straightforward SIFA attacks, which require only very limited knowledge about the concrete implementation. Therefore, the exploration of countermeasures against SIFA that do not rely on protocols or physical protection mechanisms is of great interest. In this paper, we describe different countermeasure strategies against SIFA. First, we introduce an abstraction layer between the algorithmic specification of a cipher and its implementation in hardware or software to study and describe resistance against SIFA. We then show that by basing the masked implementation on permutations as building blocks, we can build circuits that withstand single-fault SIFA and DPA attacks. We show how this approach can be applied to 3-bit, 4-bit, and 5-bit S-boxes and the AES S-box. Additionally, we present a strategy based on fine-grained fault detection suitable for protecting any circuit against SIFA attacks. Although this approach may lead to a higher implementation cost due to the fine-grained detection needed, it can be used to protect arbitrary circuits and can be generalized to cover multi-fault SIFA. For single-fault SIFA protection, our countermeasures only have a small computational overhead compared to a simple combination of masking and duplication.

Performance Analysis of Advanced Encryption Standard (AES) S-boxes

The Advanced Encryption Standard (AES) algorithm is available in a wide scope of encryption packages and is the single straightforwardly accessible cipher insisted by the National Security Agency (NSA), The Rijndael S-box is a substitution box S-Box assumes a significant job in the AES algorithm security. The quality of S-Box relies upon the plan and mathematical developments. Our paper gives an outline of AES S-Box investigation, the paper finds that algebraic attack is the most security gap of AES S-Box, likewise give a thought regarding distinctive past research to improve the static S-confines that has been utilized AES, to upgrade the quality of AES Performance by shocking the best S-box.

Design of secure cryptosystem based on chaotic components and AES S-Box

In this paper, we design, realize and evaluate a new secure cryptosystem based on a Pseudo-Chaotic Number Generator(PCNG), a global diffusion and a block cipher in Cipher Block Chaining(CBC) mode. The proposed PCNG, defined over a finite field, is based on a discrete Chebyshev map coupled with a Pseudo-Random Number Generator(PRNG) and a discrete skew tent map. Our PCNG can remove a hidden danger of deteriorated security caused by the dynamical degradation encountered in numerical implementation of chaotic maps defined on real numbers. The global diffusion uses a Horizontal Addition Diffusion(HAD) and a Vertical Addition Diffusion(VAD) followed by a modified 2-D cat map. The block cipher in CBC mode is based on a confusion layer using the AES S-Box, followed by a diffusion layer built on the modified 2-D cat map and a key addition operation. The global diffusion enhances the diffusion process of the block cipher. Conducted security analysis and the obtained results have proven that the proposed cryptosystem design is robust with high security and that it can be applied to practical implementations.

Plaintext-related image encryption algorithm based on perceptron-like network

A perceptron-like network based on integer domain was proposed, and then a new image cryptosystem based on the network was proposed in this paper. Different from the structure of classical image cryptosystem, the proposed image cryptosystem employed the perceptron-like network to achieve the diffusion of image information. It firstly generated the pseudo-random key streams from the secret key through chaotic system and S-box of AES. Then it obscured the sequence of plain image by XOR operation. Next, it used two perceptron-like networks to fulfill the information memory and diffusion of the image sequence. Finally, it obscured the diffused sequence using the equivalent keys to obtain the cipher image sequence. Performance analysis and comparison analysis show that the proposed image cryptosystem has the advantages of fast processing speed, strong system sensitivity and high security, and can be applied to the actual image communications.

Generation of Highly Nonlinear and Dynamic AES Substitution-Boxes (S-Boxes) Using Chaos-Based Rotational Matrices

This work reports a novel chaos-based affine transformation generation method, which is based on rotational matrices to design strong key-based S-boxes. Chaotic logistic map’s nonlinear trajectories are used to generate rotational matrices under given design conditions. Thus, the inherent logic is to generate key-based S-boxes, as strong as AES S-box, in terms of cryptographic properties using chaos in affine transformation. The randomness of chaotic sequences is tested using the National Institute of Standard and Technology (NIST) Statistical Test Suit (STS) 800–22 that validates the generated sequences for S-box design. The results show that methodology adapted to design proposed key-based dynamic S-boxes entails near-optimal cryptographic properties so that proposed S-boxes are as stronger as AES S-box.

Lightweight implementation of SILC, CLOC, AES-JAMBU and COLM authenticated ciphers

Authenticated encryption schemes provide both confidentiality and integrity services, simultaneously. CAESAR competition will identify a portfolio of authenticated ciphers, which is expected to be suitable for widespread adoption and offers advantages over AES-GCM. An important criterion for selecting the final candidates, besides security, is the hardware performance in resource-limited environments. In this paper, SILC, CLOC, AES-JAMBU, and COLM authenticated ciphers have been selected from the third round of the CAESAR competition for hardware evaluation. The main reasons to choose these schemes are their lightweight design, sufficient security level, and the use of the AES algorithm as their underlying block cipher. To the best our knowledge, it is the first time that an 8-bit lightweight architecture which is compatible with API v2 is presented for the selected schemes. To implement AES, the Atomic-AES v2 which is one of the smallest implementations has been adopted according to the requirements of the selected schemes. Furthermore, to reduce the area in the hardware implementation, several techniques are used, including implementing one AES core in the datapath, sharing registers to store intermediate values, implementing the tweak functions with the shuffling of wires, and implementing doubling on the GF(2128) with 8-bit architecture to construct the higher-order multipliers. The implementation results are presented on ASIC and FPGA platforms. The proposed architecture for each scheme on the two platforms is similar, but different optimization techniques are used for each platform, e.g. the AES S-box is implemented as ROM-based and logic-based on FPGA and ASIC, respectively. The comparing of the results with 128-bit implementations shows that the area on FPGA and ASIC is reduced up to 65% and 88%, respectively. The results of the current study demonstrate that AES-JAMBU has the lowest hardware area and the highest throughput and performance on both platforms. Besides, CLOC has the highest area reduction on both platforms, compared with those of the 128-bit implementations.