Advanced Solid-phase Crystallization Research Articles

N-Type Polycrystalline Germanium Layers Formed by Impurity-Doped Solid-Phase Growth

The carrier mobility of polycrystalline Ge thin-film transistors has significantly improved in recent years, raising hopes for the realization of next-generation electronic devices. Here, we adapted advanced solid-phase crystallization, which achieved the highest hole mobility of the polycrystalline semiconductor layer, to Ge layers doped with n-type impurities (P, As, and Sb). The type and amount of dopants had marked effects on the growth morphology and electrical properties of the Ge layers because they altered the activation energies in crystal growth, dopant activation rates, and grain boundary properties. In particular, P doping was effective in increasing the grain size (25 μm) and lowering the grain boundary barrier height (20 meV), which improved the electron concentration (8.0 × 1018 cm–3) and electron mobility (380 cm2 V–1 s–1) in n-type polycrystalline Ge layers. The electron mobility is greater than that of most semiconductor layers synthesized at low temperatures (≤500 °C) on insulators, and this will pave the way for advanced electronic devices, such as multifunctional displays and three-dimensional large-scale integrated circuits.

High thermoelectric power factors in polycrystalline germanium thin films

The high potential of polycrystalline Ge as a thin-film thermoelectric material was demonstrated. We synthesize a polycrystalline Ge layer on an insulating substrate at 450 °C via advanced solid-phase crystallization and control its carrier concentration through the solid-phase diffusion of various p- and n-type dopants. The heating deposition (150 °C) of the amorphous precursor considerably improves the crystal quality of the polycrystalline Ge layer as well as the doping properties. The solid-phase diffusion of Ga and P dopants onto the Ge layers allows for control of the carrier concentration in the ranges of 1017–1020 cm−3 for p-type and 1018–1019 cm−3 for n-type, respectively, by modulating the diffusion annealing temperature and time. Because of the high electrical conductivities reflecting the carrier mobilities and carrier concentrations, the maximum power factors reach a value of 1080 μW m−1 K−2 for p-type and 2300 μW m−1 K−2 for n-type at room temperature. These power factors are higher than those of most polycrystalline semiconductor thin films formed at temperatures below 1000 °C. Therefore, this study serves as a milestone toward high-performance and reliable thin-film thermoelectric generators based on an environmentally friendly semiconductor.

(Invited) Polycrystalline Ge-Based Thin Films with High Carrier Mobility

Low-temperature synthesis of high-performance semiconductor thin films on insulators is a key technology to integrate functional devices into Si-LSIs, flat panel displays, and various sensors surrounding us. Ge and Ge-based semiconductors, such as SiGe and GeSn, have higher carrier mobility and lower crystallization temperature than Si, in addition to good compatibility with conventional Si process. In recent years, Ge-MOSFET mobilities have exceeded those of Si-MOSFETs because of the development of device technologies including gate stacks. Conversely, a thin film structure is preferable to a bulk structure to suppress leakage current derived from the narrow band gap. For these reasons, Ge-based thin films are very promising as a channel material for advanced thin film transistors (TFTs). However, the performance of Ge-TFTs is currently limited by the crystallinity of the Ge thin film itself. To improve the device performance, it is essential to innovate the synthesis technology of Ge thin films on insulators.Generally, a polycrystalline Ge (poly-Ge) layer has a high hole concentration because of defect-induced acceptors and a low carrier mobility due to grain boundary scattering.1 In low-temperature (< 500 °C) solid-phase crystallization (SPC) process, we found that the densification of the amorphous Ge (a-Ge) precursor significantly enlarged the grain size and reduced the grain boundary barrier height of the resulting poly-Ge.2 Based on the finding, we have continuously updated the Hall hole mobility of Ge layers formed on insulators (Fig. 1 (a)).3,4 It is attractive that the hole mobility exceeds that of a single-crystal Si wafer, even though the Ge layers are polycrystalline formed by a simple process. The TFT based on the Ge layer exhibited the highest performance among low-temperature Ge-TFTs.5 Because the densified a-Ge crystallizes even at < 400 °C, a flexible plastic can be used for the substrate.4 An n-type poly-Ge layer with a high electron mobility is also achieved by SPC of a-Ge containing n-type dopants (Fig. 1(b)).6,7 Further, we have demonstrated that the advanced SPC technique is useful for SiGe8 and GeSn9,10 alloys. This technique may be universally applicable to other materials, and is currently being applied to III-V compound semiconductors.In this talk, I will discuss (i) the effects of density modulation and doping in Ge precursors on subsequent SPC and (ii) the composition effects of SiGe and GeSn alloys on the growth and electrical properties.[1] K. Toko et al., Solid State Electronics 53, 1159 (2009).[2] K. Toko et al., Sci. Rep. 7, 16981 (2017).[3] R. Yoshimine et al., Appl. Phys. Express 11, 031302 (2018).[4] T. Imajo et al., Appl. Phys. Express 12, 015508 (2019).[5] K. Moto et al., Appl. Phys. Lett. 114, 212107 (2019).[6] D. Takahara et al., Appl. Phys. Lett. 114, 082105 (2019).[7] M. Saito et al., Sci. Rep. 9, 16558 (2019).[8] D. Takahara et al., J. Alloys Compd. 766, 417 (2018).[9] K. Moto et al., Sci. Rep. 8, 14832 (2018).[10] K. Moto et al., Appl. Phys. Lett. 114, 112110 (2019). Figure 1

Influence of grain boundaries on the properties of polycrystalline germanium

High-speed thin film transistors based on plastic substrates are indispensable to realize next-generation flexible devices. Here, we synthesized a polycrystalline Ge layer, which had the highest quality ever, on GeO2-coated substrates using advanced solid-phase crystallization at 375 °C. X-ray diffraction and Raman spectroscopy revealed that Ge on plastic had a compressive strain, while conventional Ge with a glass substrate had a tensile strain. This behavior was explained quantitatively from the difference in the thermal expansion coefficients between Ge and the substrate. Electron backscatter diffraction analyses showed that the Ge had large grains up to 10 μm, while many intragranular grain boundaries were present. The potential barrier height of the grain boundary was lower for the plastic sample than that for the glass sample, which was discussed in terms of the strain direction. These features resulted in a hole mobility (500 cm2/V s) exceeding that of a single-crystal Si wafer. The findings and knowledge will contribute to the development of polycrystalline engineering and lead to advanced flexible electronics.

Sb-doped crystallization of densified precursor for n-type polycrystalline Ge on an insulator with high carrier mobility

Low-temperature synthesis of polycrystalline (poly-) Ge on insulators is a key technology to integrate Ge-CMOS into existing devices. However, Fermi level control in poly-Ge has been difficult because poly-Ge has remained naturally highly p-type due to its defect-induced acceptors. We investigated the formation of n-type poly-Ge (thickness: 100–500 nm) using the advanced solid-phase crystallization technique with Sb-doped densified precursors. Sb doping on the order of 1020 cm−3 facilitated lateral growth rather than nucleation in Ge, resulting in large grains exceeding 15 μm at a low growth temperature (375 °C). The subsequent heat treatment (500 °C) provided the highest electron mobility (200 cm2/V s) and the lowest electron density (5 × 1017 cm−3) among n-type poly-Ge directly grown on insulators. These findings will provide a means for the monolithic integration of high-performance Ge-CMOS into Si-LSIs and flat-panel displays.

High-hole mobility Si1-xGex (0.1 ≤ x ≤ 1) on an insulator formed by advanced solid-phase crystallization

The grain size and hole mobility of polycrystalline Si1-xGex thin films formed on glass by solid-phase crystallization were significantly improved after preparing the amorphous precursors by heating the substrate. By just controlling the deposition temperature of the precursors (50–350 °C) for each SiGe composition, the grain size reached over 2 μm across the whole composition range. Reflecting the enlargement of the grain size, the hole mobility values were improved by approximately one order of magnitude. These values are comparable to those of single-crystal SiGe formed by Ge condensation and are the highest among SiGe on insulators synthesized at low temperature (<900 °C). The SiGe on insulator technology obtained in this study will greatly contribute to the development of SiGe-based electronic and optical devices.

Advanced solid-phase crystallization for high-hole mobility (450 cm2 V−1 s−1) Ge thin film on insulator

The hole mobility of the solid-phase-crystallized Ge layer is significantly improved by controlling the deposition temperature of Ge (50–200 °C) and the Ge thickness (50–500 nm) and by applying post annealing at 500 °C. The resulting hole mobility — 450 cm2 V−1 s−1 — is the highest reported value to date among semiconductor layers directly formed on glass. The mechanism of the mobility enhancement is discussed from the perspective of three carrier scattering factors: grain boundary scattering, interface scattering, and impurity scattering. The high-hole mobility Ge layer formed via the simple fabrication process is useful for high-speed thin-film transistors.

Advanced Si solid phase crystallization for vertical channel in vertical NANDs

The advanced solid phase crystallization (SPC) method using the SiGe/Si bi-layer structure is proposed to obtain high-mobility poly-Si thin-film transistors in next generation vertical NAND (VNAND) devices. During the SPC process, the top SiGe thin film acts as a selective nucleation layer to induce surface nucleation and equiaxial microstructure. Subsequently, this SiGe thin film microstructure is propagated to the underlying Si thin film by epitaxy-like growth. The initial nucleation at the SiGe surface was clearly observed by in situ transmission electron microscopy (TEM) when heating up to 600 °C. The equiaxial microstructures of both SiGe nucleation and Si channel layers were shown in the crystallized bi-layer plan-view TEM measurements. Based on these experimental results, the large-grained and less-defective Si microstructure is expected to form near the channel region of each VNAND cell transistor, which may improve the electrical characteristics.

New Pixel Design on Emitting Area for High Resolution Active-Matrix Organic Light-Emitting Diode Displays

We propose new pixel design on emitting area and corresponding shadow mask design for high resolution active-matrix organic light-emitting diodes (AMOLEDs) to overcome the limitation of conventional shadow mask process. The proposed scheme has the extended emitting area into adjacent sub-pixel and gives flexibility for manufacturing shadow mask with quarter resolution compared with conventional requirement. The proposed scheme can use normal pixel driving circuit; however, anode electrode in each sub-pixel covers adjacent pixels to extend its own emitting aperture area for high resolution AMOLEDs. We have successfully implemented this scheme in a 4.3-in-sized WVGA (854 × RGB × 480) AMOLED using p-type advanced-solid phase crystallization (A-SPC) backplane technology and top emissive organic light-emitting diode (OLED) device structure and evaluated key performance characteristics.

Advanced Solid-Phase Crystallization of Amorphous Silicon on a Glass Substrate

Advanced Solid-Phase Crystallization of Amorphous Silicon on a Glass Substrate Thanh Nga Nguyen and Sungwook Jung School of Information and Communication Engineering, Sungkyunkwan University, Suwon 440-746 Junsin Yi School of Information and Communication Engineering and Department of Energy Science, Sungkyunkwan Unversity, Suwon 440-746 (Received 22 September 2008) We report the crystallization of an amorphous silicon (a-Si) lm by using advanced solid-phase crystallization (a-SPC). Solid-phase crystallization (SPC) is the most common method to obtain polycrystalline silicon (poly-Si). However, SPC requires a long annealing time to change from the a-Si phase to the poly-Si phase. The a-SPC method, which employs a high annealing temperature (above 700 C) but a short annealing time, is investigated to overcome this disadvantage. After dehydrogenating at 450 C for 2 hours, the a-Si lms on Corning EAGLE glass substrates are annealed by rapid thermal processing (RTP). The UV-Vis spectrum reveals that the poly-Si appears for heat-treatment at 750 C for 3 seconds. When the annealing time is increased until the critical point, at which the glass substrate bends, the crystalline fraction, as well as the quality of the poly-Si layer, improves. Raman spectroscopy con rms these results. The highest crystalline fraction is 96 % for an annealing time of 5 minutes. PACS numbers: 78.66.Jg

High-Performance Bottom-Gate TFT Fabricated by Employing SPC with Magnetically-Assisted RTA

An n-type TFT, based on the conventional a-Si TFT process, having advanced solid phase crystallization (A-SPC) with magnetically-assisted RTA has been developed on a glass substrate. Even though the A-SPC process has a temperature higher than the glass transition temperature, it showed no glass warpage but only manageable glass shrinkage, so processing on a glass substrate is possible. The n-type TFT with A-SPC process shows higher current drivability and device reliability than an a-Si TFT, which overcomes the drawbacks of a conventional a-Si TFT backplane. It also shows relatively good short-range device uniformity to solve the problem of conventional poly-Si TFTs. The n-type backplane with A-SPC technology was veri ed by manufacturing a 15-inch AMOLED panel.

9.3: 15‐inch AMOLED Display with SPC TFTs and a Symmetric Driving Method

AbstractWe have developed a new 15.0‐inch AMOLED display. An advanced Solid Phase Crystallization (a‐SPC) method was employed for the increase of uniformity and reliability of TFTs. A new pixel was proposed for the compensation of I×R voltage drop in power line and a symmetric driving scheme was also developed for the reduction of short term image sticking problem.