Adjacent Channel Leakage Power Ratio Research Articles

Effective Digital Predistortion (DPD) on a Broadband Millimeter-Wave GaN Power Amplifier Using LTE 64-QAM Waveforms

We demonstrate in this work effective linearization on a millimeter-wave (mm-Wave) broadband monolithic gallium nitride (GaN) power amplifier (PA) using digital predistortion (DPD). The PA used is a two-stage common-source (CS)/2-stack PA that operates in the mm-Wave 5G FR2 band, and it is linearized with the generalized memory polynomial (GMP) DPD and tested using 4G (4th generation) long-term-evolution (LTE) 64-QAM (quadrature amplitude modulation) modulated signals with a PAPR (peak-to-average power ratio) of 8 dB. Measurement results after implementing GMP DPD indicate considerable broadband improvement in the adjacent channel leakage power ratio (ACLR) of 16.9 dB/17.3 dB/16.5 dB/15.1 dB at 24 GHz/28 GHz/37 GHz/39 GHz, respectively, with a common average POUT of 15 dBm using a 100 MHz LTE 64-QAM input signal. At a fixed frequency of 28 GHz, the GaN PA after GMP DPD achieved signal bandwidth-dependent ACLR improvement and root-mean-square (rms) EVM (error vector magnitude) reduction using 20 MHz/40 MHz/80 MHz/100 MHz LTE 64-QAM waveforms with a common average POUT of 15 dBm. The GaN PA thus achieved very good linearization results compared to that in other state-of-the-art mm-Wave PA DPD studies in the literature, suggesting that GMP DPD should be rather effective for linearizing mm-Wave 5G broadband GaN PAs to improve POUT, Linear.

Reverberation Chamber Techniques for Determining the Adjacent Channel Leakage Power Ratio of Wireless Devices

Reverberation Chamber Techniques for Determining the Adjacent Channel Leakage Power Ratio of Wireless Devices

A Digitally assisted nonlinearity suppression architecture using over‐the‐air beam cancelation

AbstractUsing a large number of power amplifiers brings serious nonlinear distortion to 5G communication systems, which becomes a challenging problem for conventional digital predistortion (DPD) to linearize signals. To address this challenge, we propose a digitally assisted nonlinearity suppression architecture for applications in multiple antenna arrays. In this architecture, we use an auxiliary array to generate a nonlinear cancelation signal to cancel with the main beam at the receiving end. We explore a two‐step method to model the nonlinear signal and combine neural network to complete the modeling. In addition, we introduce a novel method for estimating and tracking the channel to update the model coefficients. To verify the proposed methods, we design a scene and compare the performance of our architecture with that of conventional DPD. Our experiments demonstrate that our proposed methods can significantly enhance the adjacent channel power leakage ratio performance by 12 dB while also optimizing in‐band distortion. Moreover, our architecture outperforms conventional DPD approaches even with enhanced distortion.

New Load Modulation Combiner Having a Capability of Back-Off Control for Doherty Power Amplifiers

A new load modulation combiner (LMC) having the capability of back-off control is proposed for a Doherty power amplifier (DPA). The proposed LMC consists of two transmission lines tied at the combining node, and a shunt element across the other ends of the transmission lines. The shunt element of the LMC becomes virtually open-circuited at the peak power level and allows the carrier amplifier to have an arbitrary load impedance at the low power level. The operating principle and circuit structure of the DPA based on the proposed LMC are presented in detail. The proposed DPA was implemented using GaN-HEMT for the 3.5 - 4.0 GHz band. Using a 5G NR signal with a peak-to-average power ratio (PAPR) of 7.9 dB and signal bandwidth of 100 MHz, the implemented DPA showed drain efficiency (DE) of 49.6 - 54.4% and power gain of 11.1 - 13.0 dB at an average output power of 34.5 dBm. An adjacent channel leakage power ratio (ACLR) was obtained as −50.4 - −45.0 dBc at the average power level with a digital pre-distortion (DPD) technique.

Distortion Analysis of RF Power Amplifier Using Probability Density of Input Signal and AM-AM Characteristics

When confirming the ACLR (adjacent channel leakage power ratio), which are representative indicators of distortion in the design of PA (power amplifier), it is well known how to calculate the AM-AM/PM characteristics of PA, input time series data of modulated signals, and analyze the output by Fourier analysis. In 5G (5th generation) mobile phones, not only QPSK (quadrature phase shift keying) modulation but also 16QAM (quadrature modulation), 64QAM, and 256QAM are becoming more multivalued as modulation signals. In addition, the modulation band may exceed 100MHz, and the amount of time series data increases, and the increase in calculation time becomes a problem. In order to shorten the calculation time, calculating the total amount of distortion generated by PA from the probability density of the modulation signal and the AM (amplitude modulation)-AM/PM (phase modulation) characteristics of PA is considered. For the AM-AM characteristics of PA, in this paper, IMD3 (inter modulation distortion 3) obtained from probability density and IMD3 by Fourier analysis, which are often used so long, are compared. As a result, it was confirmed that the result of probability density analysis is similar to that of Fourier analysis, when the nonlinearity is somewhat small. In addition, the agreement between the proposed method and the conventional method was confirmed with an error of about 2.0dB of ACLR using the modulation waves with a bandwidth of 5MHz, RB (resource block) being 25, and QPSK modulation.

Impact of Nonideal Auxiliary Current Profile on Linearity of Microwave Doherty Amplifiers: Theory and Experiments

A new nonlinear effect of Doherty power amplifier (DPA) caused by the nonideal auxiliary current is disclosed. In contrary to traditional assumption, the auxiliary current profile is found to be a nonlinear function of input drive. Although perfect load modulation conditions can be enforced at the transition and saturation power levels (i.e., two efficiency peaks), inside the Doherty region, the nonlinear auxiliary current incurs insufficient load modulation, leading to voltage clipping effect. Theoretical analysis reveals that the conventional design (DPA-I) can suffer from degraded linearity performance with distorted waveforms, increased harmonic regrowth, and poor phase distortion. For further investigation, a modified design (DPA-II) is contrived with remedied clipping effect. Simulation studies show that the linearity of DPA-II is largely improved with minimal reduction in efficiency, which indicates this non-ideal current profile is one of the fundamental limiting factors of DPA linearity and cannot be overlooked. For verification, two 42-dBm 2-GHz symmetrical DPAs based on GaN HEMT are designed, fabricated, and measured. Experimental results show that DPA-II provides 11-dB suppression in third-order intermodulation distortion (IMD3) and 8-dB enhancement in adjacent channel leakage power ratio (ACLR), compared to DPA-I. Meanwhile, excellent efficiency performance was attained with drain efficiency of 54%/71.5% at back-off/saturation.

Compact Load Network Having a Controlled Electrical Length for Doherty Power Amplifier

The load network of the carrier amplifier for the conventional Doherty power amplifier (DPA) consists of an impedance matching circuit, an offset line, and a λ/4 transmission line (TL), so that the overall electrical length of the network can easily exceed the minimum value of 90°. Then for appropriate impedance modulation, it should be 270° with an additional 180°. This excessive electrical length of the load matching network limits the bandwidth at either the low-power or peak-power level. In this paper, a compact quasi-lumped λ/4 impedance transformer (ITF) having simultaneous multiple functions of impedance matching and load impedance modulation with a controlled electrical length of 90° is presented. The proposed load network includes the internal components of the transistor, the simplest high-pass network using a shunt inductor, and a low-pass L-C network. Using the optimized value of the shunt inductor, the electrical length of the load network can be adjusted to 90°, while other components are accordingly changed to match the optimum load impedance. To verify the proposed load network, a DPA was designed and implemented using 10 W GaN-HEMTs for both carrier and peaking amplifiers. Using a 5G New Radio (NR) signal with signal bandwidth of 100 MHz and peak-to-average power ratio (PAPR) of 7.8 dB, a drain efficiency (DE) of 47 - 54.2%, and adjacent channel leakage power ratio (ACLR) of –27.9 - –23 dBc were achieved at an average output power level of 35.8 - 36.3 dBm for the frequency band of 3.4 - 3.8 GHz.

Generalized Expression and Design Method of Modified Load Networks for Doherty Power Amplifier With Extended Back-Off Range

This paper presents a generalized expression of the modified load networks (MLNs) for Doherty power amplifiers (DPAs) with an extended output power back-off (OBO) range. Based on the analysis using this new expression, a new circuit structure generally applicable to any combination of the multiple MLNs is proposed. The load network has a simple structure including impedance matching circuits and offset lines for the carrier and peaking amplifiers. A design procedure for the proposed load network is presented. A DPA using any optimized combination of the multiple MLNs can be easily designed using the proposed load network. For verification, a GaN-HEMT symmetrical DPA based on a combination of the virtual open-stub (VOS) and out-phased current combining (OCC) methods was designed and implemented for the frequency band of 3.4 - 3.7 GHz. The reversed uneven power splitting method is adopted in the design for higher power gain. Using the 5G New Radio (NR) signal with a peak-to average power ratio (PAPR) of 7.9 dB and a signal bandwidth of 100 MHz, the proposed DPA exhibited DE of 55.3 - 60.9% with a power gain of 11.9 - 12.7 dB at an average output power of 33.7 dBm. An adjacent channel leakage power ratio (ACLR) of -42.6 - -44.8 dBc was achieved at the average power level by using a digital predistortion (DPD) technique across the band.

Wideband 1-Bit Bandpass Delta Sigma Modulator Using Elliptic Filter in Noise Transfer Function

A 1-bit band-pass delta-sigma modulator (BP-DSM), which utilizes oversampling technology, allows a modulated signal to be directly output by using a high-speed 1-bit digital pulse train, thus realizing miniaturization of transmitters. For 1-bit BP-DSM, the noise transfer function (NTF) is used to suppress quantization noise power in the transmission band and a guideline of out-of-band gain of |NTF|< 1.5 is used to prevent oscillation. However, in previous studies, such as Butterworth and inverse Chebyshev filters, the out-of-band gain was designed indirectly by tuning the zeros and poles in the transmission band and thus, was not stabilized sufficiently. Furthermore, even though the zeros of the NTF are identical to the poles of the loop filter, there are still widely used designs in which the zeros are set on the unit circle, making stabilization quite difficult. Therefore, in this paper, we propose a feasible implementation of the NTF for 1-bit BP-DSM with an elliptic filter that can be used to set not only in-band but also out-of-band gain, in which both the zeros and poles are set inside the unit circle. As a design result, a modulation bandwidth of 400 MHz as a relative bandwidth of 11%, a noise suppression bandwidth of 800 MHz, and an adjacent channel leakage power ratio of 50 dB were achieved at a center frequency of 3.6 GHz, enabling a wider bandwidth and higher SNR than before by improving the stability.

Peak-Current-Ratio-Enhanced Compact Symmetrical Doherty Amplifier Design by Using Active Harmonic Control

This article proposes a new and compact symmetrical Doherty power amplifier (DPA) configuration that provides extended output-back-off (OBO) and enhanced load modulation. The concept of active harmonic control (AHC) is introduced to remedy the reduced-conduction-angle operation of the class-C auxiliary device, providing enhanced auxiliary current and power capability. Semianalytical study based on generalized load-modulation theory and large-signal simulation reveal that an optimal AHC can offer increased peak current ratio, improved load modulation, boosted output power, and power utilization factor (PUF). Besides, a new output combiner, with the inclusion of parasitic effect, is devised for ultracompactness and simplicity. For verification, a 11-dB-OBO 2-GHz symmetrical DPA based on GaN HEMT transistors is designed, fabricated, and measured. Excellent performance with drain efficiency of 74% (52%) is obtained at saturation (back-off of 11 dB). Moreover, a saturation power of 42.98 dBm is achieved, corresponding to an uplifted PUF of 1.25 (compared with conventional symmetrical DPA design). Under 20-MHz modulated signal (peak-to-average power ratio of 11 dB) excitation, the prototype exhibits average efficiency of 53.2% at an average output power of 32 dBm. The adjacent channel leakage power ratio (ACLR) is found to be −27.5 and −50.9 dBc before and after digital predistortion, respectively.

Doherty Power Amplifier Based on Asymmetric Cells With Complex Combining Load

This article presents a Doherty power amplifier (DPA) based on asymmetric cells with a complex combining load (CCL). In this study, a new and intuitive design technique using the Smith chart is proposed for developing the load network of the CCL-DPA. The peaking amplifier consists of a larger cell size compared to that of the carrier amplifier in order to achieve higher power gain and peak output power in comparison with the conventional CCL-DPAs based on symmetric cells. For verification purposes, the proposed asymmetric CCL-DPA was designed and implemented using 6- and 10-W GaN-HEMTs for the carrier and peaking amplifiers, respectively. For the 1.68-GHz continuous-wave signal, the asymmetric CCL-DPA exhibited a power-added efficiency (PAE) of 68.0% and a drain efficiency (DE) of 73.9% at a peak output power of 43.5 dBm. When an output power back-off of 9.5 dB was used, a PAE of 52.0% and a DE of 54.7% were achieved. Using the long-term evolution signal with a peak-to-average power ratio of 9.6 dB and a signal bandwidth of 10 MHz, a PAE of 53.6%, a DE of 56.4%, and a power gain of 13.5 dB were obtained at a power level of 34.0 dBm. Using a digital predistortion technique, an adjacent channel leakage power ratio of -48 dBc was achieved at the same power level.

Optimized Broadband Load Network for Doherty Power Amplifier Based on Bandwidth Balancing

This letter presents an optimized broadband load network for the Doherty power amplifier (DPA) based on bandwidth balancing between low- and peak-power levels. The optimized broadband load network is composed of a quasi-lumped $\lambda $ /4 impedance transformer (ITF), a modified multiple resonance circuit (MMRC), and a broadband postmatching network (PMN). The quasi-lumped ITF at the carrier amplifier has an optimized characteristic impedance for bandwidth balancing between low- and peak-power levels. The MMRC provides the quasi-lumped ITF with an appropriate susceptance for optimized bandwidth. It also matches the impedance for the peaking amplifier. To validate this design concept, the broadband DPA was implemented using 30-W gallium–nitride high electron mobility transistor (GaN-HEMT) for both carrier and peaking amplifiers. For the down-link long-term evolution (LTE) signal with a channel bandwidth of 10 MHz and a peak-to-average power ratio (PAPR) of 6.5 dB at the frequency range of 1.15–2.45 GHz, DE ranging from 38.4% to 52.2%, and the adjacent channel leakage power ratio (ACLR) ranging from −23.9 to −35.0 dBc at an average output power of from 39.7 to 41.7 dBm were achieved.

Wideband Two-Way Hybrid Doherty Outphasing Power Amplifier

A new type of wideband dual-input hybrid Doherty outphasing power amplifier (HDO-PA) is developed in which the load-modulation scheme continuously converts as the frequency increase, from the previously reported HDO-PA mode with maximum flat efficiency response versus power to the conventional Doherty PA mode. For a symmetric HDO-PA implementation, this corresponds to the peak-to-backoff fundamental voltage ratio of the auxiliary amplifier linearly varying from 9/7 to 2 with frequency. A transmission-line-based wideband HDO-PA prototype is first established at the current-source reference planes to cover the frequency band from 1.4-GHz to 2.5-GHz. The wideband HDO-PA is implemented next at the package reference planes by synthesizing the wideband combiner circuit required to sustain the intrinsic load-modulation behavior across the entire frequency bandwidth. A 1.4-GHz to 2.5-GHz wideband HDO-PA is fabricated and characterized using both continuous-wave and modulated signals. The 6-dB backoff efficiency varies from 60% to 44% and the maximum power from 44.8 dBm to 42.9 dBm as the frequency increases. When the PA is excited with a 20 MHz bandwidth long-term evolution signal at 1.7 GHz with 6.5 dB peak-to-average-power ratio (PAPR), the PA achieves an average drain efficiency of 50.3% with -32.0 dBc adjacent-channel-power leakage ratio (ACLR) and an average drain efficiency of 47.8% with -54.0 dBc ACLR after digital predistortion linearization.

A Highly Extended High-Efficiency Range Class-F–C Doherty Power Amplifier

This paper presents a new extended high-efficiency-range Doherty power amplifier (DPA) with a main and only a single auxiliary amplifier. In order to extend the output high-efficiency range with a high-efficiency level, asymmetrical cells are employed as the main and auxiliary amplifiers in class-F and class-C complex combining load (CCL) methodology, respectively. To verify the proposed methodology, a DPA with 12-dB output back-off (OBO) is designed and fabricated for wideband code division multiple access (WCDMA) applications. Large-signal continuous-wave measurement results show the power gain of about 11[Formula: see text]dB with a drain efficiency of 59.9% at 12[Formula: see text]dB of OBO. A two-tone test exhibits a third-order intermodulation distortion (IMD) of lower than [Formula: see text][Formula: see text]dBc. Modulated wave measurements show over 55% of average drain efficiency and an adjacent channel leakage power ratio (ACLR) of lower than [Formula: see text][Formula: see text]dBc at an output power level of 31.5[Formula: see text]dBm.

Broadband InGaP/GaAs HBT Power Amplifier Integrated Circuit Using Cascode Structure and Optimized Shunt Inductor

This article presents a broadband two-stage cascode power amplifier integrated circuit (PAIC) using a 2- $\mu \text{m}$ InGaP/GaAs heterojunction bipolar transistor process. Since higher supply voltage of cascode power amplifier (PA) results in lower impedance transformation ratio of the matching network due to lower current, cascode PAs generally have broader bandwidth than common-emitter (CE) PAs. However, bandwidth analysis for handset PAs with a single-section load matching network, including transistors output capacitance, revealed that cascode PAs had bandwidth similar to CE PAs. Through bandwidth analysis based on power and efficiency contours at the internal plane of the transistor, an optimized shunt inductor with a single-section load matching network was proposed in this article to increase the bandwidth of cascode PA. Performances of both cascode and CE PAs with and without the optimized shunt inductor were compared. A broadband two-stage cascode PAIC with a compensating shunt inductor and an L-section matching network was designed and implemented. The implemented PAIC exhibited an output power of at least 30.1 dBm at frequency band ranging from 1.55 to 2.65 GHz for continuous-wave excitation. Using a long-term evolution signal with a peak-to-average power ratio of 7.5 dB and a signal bandwidth of 10 MHz, a power gain of more than 23.7 dB, power-added efficiency of 30.9% to 38.4%, and average output power of 26.7 to 27.7 dBm were obtained at a given adjacent channel leakage power ratio of −30 dBc. A fractional bandwidth was calculated to be 54.3% based on measured results.

Accelerated Design Methodology for Dual-Input Doherty Power Amplifiers

A novel design theory and the methodology are presented for dual-input Doherty power amplifiers (DPAs) in which the auxiliary transistor does not fully turn off at backoff power. Given the input parameters selected by the PA designer, a Doherty load modulation behavior is exactly implemented at the current-source reference planes of the transistors by solving for the characteristic impedance of the Doherty quarter-wave transformer and the common load. The Doherty output combiner at the package reference plane that sustains the desired dual-input DPA performance is then synthesized using nonlinear embedding and exactly implemented with a lossless and reciprocal circuit. The new analytic DPA design theory also provides an expanded design space, which facilitates the selection of the optimal design based on the gain, linearity, and efficiency tradeoff. The design methodology is implemented in a software program to enable the automatic design of a dual-input DPA prototype at the package reference planes within 24 s. To validate the theory and the design methodology, a 2-GHz dual-input asymmetric DPA is fabricated and measured. When excited with a 20-MHz local thermal equilibrium (LTE) signal with 9.55-dB peak-to-average power ratio (PAPR), the DPA achieves an average power-added efficiency (PAE) of 51.6% with an adjacent-channel-power-leakage ratio (ACLR) of −47.1 dBc after linearization.

Novel Outphasing Power Amplifiers Designed With an Analytic Generalized Doherty–Chireix Continuum Theory

An analytic theory for dual-input outphasing power amplifiers that incorporate in one unified treatment, the continuum of solutions for power combining including the Doherty and Chireix modes is presented. This unified theory developed at the current-source reference planes reveals the performance trade-off achieved by all of the possible power amplifier (PA) combiners within the continuum of solutions. Furthermore, it identifies a novel type of dual-input hybrid Chireix–Doherty PA that combines key features of the Doherty and Chireix operations such that the fundamental drain voltages applied to both the main and auxiliary transistors remain constant. This hybrid PA relies on an input outphasing angle varying with the input power level to obtain the correct load modulation behavior. A 2-GHz dual-input hybrid Chireix–Doherty PA is implemented using nonlinear embedding and experimentally evaluated to validate the theory. A drain efficiency of 61% at 9-dB backoff power and a maximum output power of about 43 dBm are obtained for continuous-wave (CW) measurements. The efficiency increases monotonously with output power unlike that of the Doherty PA used for comparison. When excited with a 20-MHz LTE signal with 9.5-dB peak-to-average power ratio (PAPR), the dual-input PA yields a 60.0% average drain efficiency and −48.1-dBc adjacent-channel power-leakage ratio (ACLR) after linearization.

DSS modulator using the SIDO dc−dc converter for the CMOS RF PA integrated circuit

A dynamic supply switching (DSS) modulator using a single-inductor dual-output (SIDO) dc−dc converter for complimentary metal-oxide semiconductor (CMOS) radio frequency (RF) power amplifier (PA) integrated circuits is presented. The DSS modulator consists of the SIDO dc−dc converter and a supply switching circuit (SSC). The SIDO dc−dc converter requires only one off-chip inductor while generating two of the dc voltages. The SSC dynamically switches the high and low dc voltages according to the modulated signal envelope. The supply switching control voltage, which is generated from the envelope, is optimised for maximum efficiency improvement. The proposed DSS PA using the SIDO dc−dc converter and the SSC was fabricated using a 0.18 μm CMOS process for a 1.75 GHz frequency band and a long-term evolution (LTE) application. For the LTE 16-QAM signal with the peak-to-average power ratio (PAPR) of 7.5 dB, the measured efficiency of the DSS PA is 33.8% at the average output power of 21 dBm, thereby satisfying the adjacent channel leakage power ratio (ACLR) level of −30.1 dBc. The measured efficiency of the DSS PA at an average output power of 15 dBm is 24.8%, which is higher than that of the stand-alone PA by 13.3%.

Octave Bandwidth Doherty Power Amplifier Using Multiple Resonance Circuit for the Peaking Amplifier

This paper presents a broadband Doherty power amplifier (DPA) design with an octave bandwidth based on a new load network consisting of a quasi-lumped impedance transformer for the carrier amplifier, a multiple resonance circuit for the peaking amplifier, and a broadband post-matching network. The quasi-lumped impedance transformer and the multiple resonance circuit were designed based on accurate equivalent circuits for internal components inside the packaged transistor. Based on power bandwidth analysis, optimum susceptance provided by the multiple resonance circuit at the peaking amplifier, was obtained. The proposed broadband DPA was designed using 45 W gallium-nitride high electron mobility transistor for both carrier and peaking amplifiers. For continuous-wave signals in frequency range of 0.9 to 1.8 GHz, the implemented broadband DPA exhibited a drain efficiency of 54.2% to 73.4% at peak output power of 49.7 to 51.4 dBm and a drain efficiency of 41.7% to 58.0% at output back-off of 6 dB. For the down-link long-term evolution signal with a channel bandwidth of 10 MHz and a peak-to-average power ratio of 6.5 dB, a drain efficiency of 41.3% to 57.4% and an adjacent channel leakage power ratio of -22.5 to -30.2 dBc at an average output power of 43.2 to 449 dBm were achieved at an octave bandwidth.

Dual-Mode CMOS Power Amplifier Based on Load-Impedance Modulation

This letter presents a dual-mode CMOS power amplifier (PA) that has an improved efficiency using load-impedance modulation in the low-power mode (LPM) and a fully differential operation in the high-power mode (HPM). For the LPM, the transistor in the negative path of the differential pair is turned ON, as a switch, to appropriately modulate the load impedance for the transistor in the positive path using the output balun. An external switch is deployed to turn $V_{\text {DD}}$ OFF for the negative path. In order to verify the proposed concept, a dual-mode CMOS PA IC was designed using a bulk CMOS process and an off-chip output balun, and it was evaluated using the 920-MHz narrow-band Internet of Things signal with a bandwidth of 200 kHz and a peak-to-average power ratio of 5.7 dB. For the HPM, the implemented PA exhibited a gain of 24.1 dB, a power-added efficiency (PAE) of 44.3%, and an adjacent channel leakage power ratio (ACLR) of −33.9 dBc at an average output power of 27.7 dBm. For the LPM, a gain of 19.3 dB, a PAE of 37.7%, and an ACLR of −34.9 dBc were obtained at an average output power of 21.7 dBm.