Adiabatic Quantum-flux-parametron Gates Research Articles

Transmission Line Effects of Long Gate-to-Gate Interconnections in Adiabatic Quantum-Flux-Parametron Logic Circuits

Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family that utilizes adiabatic switching of logic gates. At present, a pure inductance is used to model a gate-to-gate interconnection in AQFP logic circuits. However, it is necessary to consider the transmission line effects when the interconnection length becomes long to take into account the propagation delay. This study investigated the transmission line effects of a long gate-to-gate interconnection in AQFP logic circuits. We observed reflection effects in a long transmission line between AQFP gates. These effects induced errors when the interconnection length exceeded several hundred micrometers. We adopted a damping resistance to stabilize the reflection effect to realize an error-free long gate-to-gate interconnection. The circuit simulations confirmed that a damping resistance connected in parallel to the transmission line effectively stabilizes the reflection effect, enabling an interconnection length that is longer than 1 mm. We fabricated AQFP buffer chains that included a long transmission line with and without a parallel damping resistance, and measured their bit error rates. The results showed that the parallel damping resistance effectively improves the bit error rate at high frequencies.

A High-Speed Interface Based on a Josephson Latching Driver for Adiabatic Quantum-Flux-Parametron Logic

The adiabatic quantum flux parametron (AQFP) is an energy-efficient, high-speed superconducting logic device. To observe the tiny output currents from the AQFP in experiments, high-speed voltage drivers are indispensable. In the present study, we develop a compact voltage driver for AQFP logic based on a Josephson latching driver (JLD), which has been used as a high-speed driver for rapid single-flux-quantum (RSFQ) logic. In the JLD-based voltage driver, the signal currents of AQFP gates are converted into gap-voltage-level signals via an AQFP/RSFQ interface and a four-junction logic gate. Furthermore, this voltage driver includes only 15 Josephson junctions, which is much fewer than in the case for the previously designed driver based on dc superconducting quantum interference devices (60 junctions). In measurement, we successfully operate the JLD-based voltage driver up to 4 GHz. We also evaluate the bit error rate (BER) of the driver and find that the BER is 7.92×10-10 and 2.67×10-3 at 1 GHz and 4 GHz, respectively.

Impedance Design of Excitation Lines in Adiabatic Quantum-Flux-Parametron Logic Using InductEx

The adiabatic quantum-flux-parametron (AQFP) is an energy-efficient superconductor logic family that utilizes adiabatic switching. AQFP gates are powered and clocked by ac excitation current; thus, to operate AQFP circuits at high clock frequencies, it is required to carefully design the characteristic impedance of excitation lines (especially, above AQFP gates) so that microwave excitation current can propagate without reflections in the entire circuit. In the present study, we design the characteristic impedance of the excitation line using InductEx, which is a three-dimensional parameter extractor for superconductor devices. We adjust the width of an excitation line using InductEx such that the characteristic impedance becomes 50 {\Omega} even above an AQFP gate. Then, we fabricate test circuits to verify the impedance of the excitation line. We measure the impedance using the time domain reflectometry (TDR). We also measure the S parameters of the excitation line to investigate the maximum available clock frequency. Our experimental results indicate that the characteristic impedance of the excitation line agrees well with the design value even above AQFP gates, and that clock frequencies beyond 5 GHz are available in large-scale AQFP circuits.

SystemVerilog Modeling of SFQ and AQFP Circuits

Exascale computing and its associated increasingly massive amounts of data require increasingly efficient computing platforms; and semiconductor technology is struggling to keep up. Meanwhile, superconducting electronics (SCE) is increasingly gaining interest in both industry and academia as a serious contender to replace silicon for supercomputing. In particular, nonresistively biased single-flux quantum (SFQ) circuits have a theoretical potential of three orders of magnitude reduction in power accompanied with one order of magnitude of higher speed, and adiabatic quantum-flux-parametron (AQFP) circuits possess a theoretical potential of six orders of magnitude reduction in power when compared to the state-of-the-art semiconductor circuits. Unfortunately, the SCE community lacks a reliable design flow. Rather than creating a complete design flow from scratch, it is often more efficient to reuse well-established semiconductor tool flows developed by EDA companies that have benefited from research and development over the past half-century. One of the components of this flow is the hardware description language (HDL) modeling of gates for behavioral and functional simulation of large netlists. The previous HDL models proposed for SCE lack modularity are not compatible with existing CMOS standards, and are overly complex. This article presents SystemVerilog models for SFQ and AQFP gates and the circuits that interface between them. Our models are compatible with standard delay format and commercial simulators. They offer a generalizable modular debugging platform, are elegant and conceptual, and can capture many circuit parameters, environmental effects, and advanced SCE phenomena.

Design and Demonstration of an Adiabatic-Quantum-Flux-Parametron Field-Programmable Gate Array Using Josephson-CMOS Hybrid Memories

Adiabatic quantum-flux-parametron (AQFP) logic is a promising technology for future energy-efficient high-performance information processing systems. Its static power is zero because of ac flux bias, and its dynamic power is considerably reduced, thanks to the adiabatic switching of the junctions. The lack of high-density memories in the AQFP logic, however, makes it challenging to realize large-scale information processing systems with the use of pure AQFP circuits. We have been developing a Josephson-CMOS hybrid memory to overcome the memory bottleneck in AQFP digital systems. By utilizing the high sensitivity of the AQFP gate, the output current from CMOS memories can be significantly decreased resulting in the reduction of the power consumption. In this article, we designed and fabricated a low-power area-efficient AQFP-CMOS hybrid field-programmable gate array (FPGA), where a CMOS memory is utilized as a rewritable read-only memory to control the AQFP circuits. The AQFP circuit for the AQFP-CMOS hybrid FPGA is composed of logic blocks, switch blocks, and connection blocks, which are clocked by four-phase excitation currents. The AQFP-CMOS hybrid FPGA is fabricated by using the AIST 10 kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> Nb high-speed standard process and the Rohm 0.18 μm CMOS process. The area and power consumption of the two-by-two AQFP logic-cell system are estimated to be approximately 6.56 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 12.4 nW at 5 GHz operations, respectively. The power consumption of the CMOS memory was estimated to be 1.02 μW assuming the CMOS source voltage of 3 mV. We demonstrated the operation of the AQFP-CMOS hybrid FPGA at low speed by combining the AQFP logic and the CMOS memory.

Low-latency adiabatic superconductor logic using delay-line clocking

Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family. The switching energy of an AQFP gate can be arbitrarily reduced via adiabatic switching. However, AQFP logic has somewhat long latency due to the multiphase clocking scheme, in which each logic operation requires a quarter clock cycle. The latency in AQFP logic should be improved in order to design complex digital circuits such as microprocessors. In the present paper, we propose a low-latency clocking scheme for AQFP logic, which we call delay-line clocking. In delay-line clocking, the latency for each logic operation is determined by the propagation delay of the excitation current, which can be much shorter than a quarter clock cycle. Our numerical simulation shows that AQFP gates can operate with a latency of only a few picoseconds. We fabricated an AQFP circuit adopting delay-line clocking using the 10 kA/cm2 Nb high-speed standard process provided by the National Institute of Advanced Industrial Science and Technology. The circuit was demonstrated at 4 GHz with a latency of 10 ps per gate. The above results indicate that delay-line clocking can significantly reduce the latency in AQFP logic.

An adiabatic superconductor 8-bit adder with 24kBT energy dissipation per junction

Adiabatic quantum-flux-parametron (AQFP) logic is an energy-efficient superconductor logic family. In this paper, we conducted the high-frequency operation and energy measurement of an AQFP circuit with more than 1000 Josephson junctions in the experiment. We designed an 8-bit carry look-ahead adder (CLA) using AQFP gates and fabricated it using an advanced fabrication technology, the AIST 10 kA/cm2 Nb high-speed standard process. The correct operation of the 8-bit CLA was demonstrated at a 1-GHz clock frequency for a critical carry propagation test vector. The energy dissipation of the 8-bit CLA was measured by observing the power of excitation current. Our results showed that the energy dissipation per operation of the 8-bit CLA can be estimated to be approximately 1.5 aJ, or 24kBT per junction, where kB is the Boltzmann constant and T is the operating temperature.

A random-access-memory cell based on quantum flux parametron with three control lines

In this study, we proposed a random-access memory (RAM) cell composed of adiabatic quantum-flux-parametron (AQFP) circuits as a component of large-scale AQFP RAMs. The memory cell is composed of a storage QFP gate and a readout AQFP gate, which is controlled by three control currents Id, Iy and Ix. Id is used to control an input datum. Iy is a column selection current for the write operation. Ix is a row selection current for both write and read operations. The control current margins evaluated in the simulation are larger than +/- 30%. We designed the memory cell of the size of 50 μm × 40 μm by using AIST high-speed standard process, and verified the correctness of its operation by experiments. It was shown that the amplitude of the control currents is compatible with the output currents of AQFP logic.

超低電力マイクロプロセッサの実現に向けた 断熱型磁束量子パラメトロンの進展

We report recent progress on adiabatic quantum-flux-parametron (AQFP) logic, which is an energy-efficient superconductor logic based on quantum flux parametron (QFP). The switching energy of an AQFP gate can be arbitrarily reduced via adiabatic switching, in which the shape of the potential energy gradually varies between single-well and double-well shapes as the result of using ac excitation magnetic fluxes. First, we show the operation principle of AQFP and explain adiabatic switching in light of potential energy shapes. We also show calculated switching energy and bit error rates to demonstrate that the switching energy of AQFP can be significantly reduced while keeping a low error rate. Then, we report recently developed AQFP subsystems, which include an 8-bit carry look-ahead adder, a register file, and a long-interconnect driver. Our demonstration reveals that AQFP technology is ready to be applied in microprocessor design.

Design and Demonstration of Interface Circuits Between Rapid Single-Flux-Quantum and Adiabatic Quantum-Flux-Parametron Circuits

We investigated interface circuits between rapid single-flux-quantum (RSFQ) circuits and adiabatic quantum-flux-parametron (AQFP) circuits for a high-speed and low-power hybrid computing system. In addition, the interface circuits allow us to use long-distance interconnections based on single-flux-quantum (SFQ) passive transmission lines between AQFP gates. The target frequency of interface circuits is several gigahertz. There are two types of interface circuits. The RSFQ/AQFP interface circuit, which transmits a signal from RSFQ circuits to AQFP gates, was realized by coupling an RSFQ toggle flip-flop (TFF) to an AQFP buffer gate. The simulated bias margins of the RSFQ TFF and the excitation current margin of the RSFQ/AQFP interface were 2.22 mA ± 24.7% and 1.71 mA ± 25.0%, respectively. The AQFP/RSFQ interface circuit, which transmits a signal from AQFP gates to RSFQ circuits, was designed by using a high-sensitive magnetically coupled dc/SFQ converter (MC-dc/SFQ) to detect an output current of an AQFP buffer gate. The simulated bias margins of the MC-dc/SFQ and the excitation current margin of the AQFP/RSFQ interface were 0.558 mA ± 20.5% and 1.95 mA ± 36.1%, respectively. We also fabricated and measured the interface circuits.

Demonstration of Signal Transmission between Adiabatic Quantum-Flux-Parametrons and Rapid Single-Flux-Quantum Circuits Using Superconductive Microstrip Lines

We have been investigating interface circuits between rapid single-flux-quantum circuits and adiabatic quantum-flux-parametron (AQFP) circuits for use in high-speed low-power hybrid computing system. These interface circuits also enable us to use long-distance interconnections between AQFP gates. In this study, we fabricated and demonstrated AQFP circuits, including long interconnections of passive transmission lines (PTLs), in which the interface circuits were used to convert the signal currents of the AQFP gates into single-flux-quantum pulses traveling along PTLs. The length of each PTL was approximately 4.3 mm. During low-speed measurements, correct operations with wide bias margins were confirmed.

High-Speed Experimental Demonstration of Adiabatic Quantum-Flux-Parametron Gates Using Quantum-Flux-Latches

We experimentally demonstrated high-speed logic operations of adiabatic quantum-flux-parametron (AQFP) gates through the use of quantum-flux-latches (QFLs). In QFL-based high-speed test circuits (QHTCs), the output data of the circuits under test (CUTs), which are driven by high-speed excitation currents, are stored in QFLs and are slowly read out using low-speed excitation currents. We designed and fabricated three types of QHTCs using QFLs with different circuit parameters, where the CUTs were buffer gates and and gates. We confirmed the correct operation of buffer gates and and gates at 1 GHz. The obtained bias margins of the 1 GHz excitation currents were more than ±30% for each QHTC, which is wide enough for high-speed logic operations of AQFP gates.

Margin and Energy Dissipation of Adiabatic Quantum-Flux-Parametron Logic at Finite Temperature

We optimized the circuit parameters of a low-power adiabatic quantum-flux-parametron (AQFP) gate in terms of both bit energy and bias margin and confirmed that the bit energy of the optimized gate with a rise time of 200 ps can be decreased to 6% of IcΦ0, where Ic is the critical current of the Josephson junctions and Φ0 is the single flux quantum. In addition, we investigated the effect of thermal noise on the operation of the optimized AQFP gate. The bias margins and bit error rate of the AQFP gate were examined at finite temperature through circuit simulations, in which the thermal noise was taken into account using the Monte Carlo method. The bias margin of the AQFP gate with bias margins of ±26% at zero temperature shrunk to ±19.4% at 4.2 K, but is still large enough for circuit applications.

Design and demonstration of an on-chip AC power source for adiabatic quantum-flux-parametron logic

Adiabatic quantum-flux-parametron (AQFP) logic is a promising technology for use in future high-end computers because its bit energy can be potentially reduced to the order of thermal energy. AQFP gates are driven by an AC bias current, which changes their potential energy adiabatically. In the present paper, we propose an on-chip AC power source, which is composed of a Josephson relaxation oscillator and a superconducting resonator, to drive the AQFP gates. We designed and implemented the AC power source using a Nb Josephson integrated circuit process. We confirmed that the AC power source can generate a 4.4 GHz sinusoidal current from a DC bias current and that the output amplitude of the AC power source can be controlled by varying the DC bias current.

Measurement of 10 zJ energy dissipation of adiabatic quantum-flux-parametron logic using a superconducting resonator

Adiabatic quantum-flux-parametron (AQFP) logic has the potential to operate with an ultimately small bit energy of several zeptojoules; however, this is too small to measure by conventional techniques. We measure such a small energy dissipation by coupling a superconducting resonator with an AQFP gate, where the insertion loss is sensitively varied with the small dissipation due to the very high Q factor of the resonator. We designed and implemented a 5 GHz superconducting resonator coupled with an AQFP gate. Measurement results show that the bit energy of the gate is ∼10 zJ at 5 GHz operation.