Addressable Non-volatile Memory Research Articles

Observation of Optically Addressable Nonvolatile Memory in VO2 at Room Temperature

AbstractVanadium dioxide (VO2) is a phase change material that can reversibly change between high and low resistivity states through electronic and structural phase transitions. Thus far, VO2 memory devices have essentially been volatile at room temperature, and nonvolatile memory has required non‐ambient surroundings (e.g., elevated temperatures, electrolytes) and long write times. For the first time, here, the authors report the observation of optically addressable nonvolatile memory in VO2 at room temperature with a readout by voltage oscillations. The read and write times have to be kept shorter than about 150 µs. The writing of the memory and onset of the voltage oscillations have a minimum optical power threshold. Although the physical mechanisms underlying this memory effect require further investigations, this discovery illustrates the potential of VO2 for new computing devices and architectures, such as artificial neurons and oscillatory neural networks.

Two-pulse sub-ns switching scheme for advanced spin-orbit torque MRAM

The steady increase in performance and speed of modern integrated circuits is continuously supported by constant miniaturization of complementary metal-oxide semiconductor (CMOS) devices. However, a rapid growth of the dynamic and stand-by power due to transistor leakages becomes a pressing issue. A promising way to slow down this trend is to introduce non-volatility in circuits. The development of an electrically addressable non-volatile memory combining high speed and high endurance is essential to achieve these goals. To further reduce the energy consumption, it is essential to replace SRAM in modern hierarchical multi-level processor memory structures with a non-volatile memory technology. The spin-orbit torque magnetic random access memory (SOT-MRAM) combines non-volatility, high speed, and high endurance and is thus suitable for applications in caches. However, its development is still hindered by relatively high switching currents and the need of an external magnetic field for deterministic switching of perpendicularly magnetized layers. The switching by means of two orthogonal current pulses allows achieving deterministic sub-500 ps and magnetic field-free switching in perpendicularly magnetized rectangular structures. Complementing the two-pulse switching scheme with weak perpendicular interface-induced magnetic anisotropy reduces the switching current significantly for achieving sub-500 ps switching in in-plane structures.

Ultra-Fast Switching of a Free Magnetic Layer with out-of-Plane Magnetization in Spin-Orbit Torque Mram Cells

Continuous miniaturization of complementary metal-oxide semiconductor (CMOS) devices is one of the driving forces for the unprecedented increase of speed and performance delivered by modern integrated circuits However, a rapid increase of the stand-by power due to transistor leakages and the need to refresh the data in dynamic random access memory (DRAM) is becoming a pressing issue. The microelectronics industry is facing major challenges related to power dissipation and energy consumption, and the microprocessors’ scaling will hit a power wall soon. An attractive path to mitigate the unfavorable trend of increasing power at stand-by is to introduce non-volatility in the circuits. The development of an electrically addressable non-volatile memory which combines fast operation, simple structure, and high endurance is essential to mitigate the increase of the stand-by power and to introduce instant-on architectures without the need of data initialization when going from a stand-by to an operation regime. Oxide-based resistive RAM (RRAM) possesses filamentary switching between on/off states and is thus intrinsically prone to significant resistance fluctuations in both on and off states. In addition, the endurance reported is only slightly higher than that in flash memory. For this reason, it is premature to consider RRAM at its current stage of development for digital applications. Since continuous conductance modulation is suitable for implementing analog synaptic weights, both filamentary and non-filamentary switching RRAM types are currently intensively investigated, particularly also for neuromorphic applications [1]. Spin-transfer torque magnetic RAM (STT-MRAM) is fast (10ns), possesses high endurance (1012), and a simple structure. It is compatible with CMOS and can be straightforwardly embedded in circuits, e.g. [2]. High-density STT-MRAM arrays with 4Gbit capacities have been already demonstrated [3]. The availability of high-capacity non-volatile memory positioned close to high-performance CMOS circuits opens a new horizon in exploring conceptually new logic-in-memory [4] and computing-in-memory architectures for future artificial intelligence and cognitive computing. Although it might be possible to introduce STT-MRAM in L3 caches, the memory is too slow for entering L1 and L2 caches currently mastered by static RAM (SRAM). In addition, rapidly increasing critical currents for switching STT-MRAM at 5ns and faster reduce the endurance to that of the flash memory. The development of an electrically addressable non-volatile memory combining high speed (sub-ns operation) and high endurance is essential for replacing SRAM) in high-level caches of hierarchical multi-level processor memory structures with a non-volatile memory [4]. The spin-orbit torque MRAM (SOT-MRAM) with perpendicular magnetization combines non-volatility, high speed, and high endurance, which makes it suitable for applications in caches [5]. However, its development is still hindered by the need of an external magnetic field to guarantee deterministic switching [6]. We apply the two-pulse scheme previously proposed for switching of an in-plane structure [7]. The SOT due to the first 100ps pulse tilts the magnetization of the free layer in-plane perpendicular to the direction of the “Write pulse 1” (Fig.1). The SOT of the second consecutive pulse results in an additional precession of the magnetization in the part of the free layer under it, which is transferred to the remaining part of the free layer through the exchange interaction. Depending on the spin of this precession, the magnetization of the remaining part tilts up or down with respect to the in-plane orientation. The part under the wire of “Write pulse 2” follows the precession after the current is turned off, thus completing the switching. Results of the switching time calculations for several pulse durations as a function of the width of the second pulse wire are shown in Fig.2. We conclude that the fastest, sub-300ps switching, is achieved at around 30% overlap of the second pulse wire with the free layer. REFERENCES G.W. Burr, R.M. Shelby, A.Sebastian et al., “Neuromorphic Computing Using Non-volatile Memory”, Advances in Physics:X 2, 89 (2017).D.Apalkov, B.Dieny, J.M. Slaughter, “Magnetoresistive Random Access Memory”, Proceedings of the IEEE 104, 1796 (2016).S.-W. Chung, T.Kishi, J. W. Park et al.,“ 4Gbit Density STT-MRAM Using Perpendicular MTJ Realized with Compact Cell Structure”, IEDM 2016 Techn. Digest, 660.T.Hanyu, T.Endoh, D.Suzuki, H.Koike, et al. “Standby-Power-Free Integrated Circuits Using MTJ-Based VLSI Computing”, Proceedings IEEE 104, 1844 (2016).S.-W. Lee and K.-J. Lee, “Emerging Three-Terminal Magnetic Memory Devices”, Proceedings IEEE 104, 1831 (2016).S.Fukami, T.Anekawa, C.Zhan, et al. “A Spin–orbit Torque Switching Scheme with Collinear Magnetic Easy Axis and Current Configuration“, Nature Nanotechnology 11, 621 (2016)A.Makarov, T.Windbacher, V.Sverdlov, and S.Selberherr, “CMOS-compatible Spintronic Devices: A Review” Semiconductor Science and Technology 31, 113006 (2016). Figure 1

Ultra-Fast Switching of a Free Magnetic Layer with Out-of-Plane Magnetization in Spin-Orbit Torque MRAM Cells

The steady increase in performance and speed of modern integrated circuits is continuously supported by constant miniaturization of complementary metal-oxide semiconductor devices. However, the rapid growth of the dynamic and stand-by power due to transistor leakages becomes a pressing issue. A promising way to interrupt this trend is to introduce non-volatility. The development of an electrically addressable non-volatile memory combining high speed and high endurance is essential for achieving these goals. The perpendicular spin-orbit torque magnetic random access memory (SOT-MRAM) combines non-volatility, high speed, and high endurance and is thus suitable for applications in caches. However, its development is still hindered by the necessity of a static in-plane magnetic field. We propose a magnetic field-free perpendicular SOT-MRAM, operated by two consecutive perpendicular current pulses, which is fast and, most importantly, does not require an external magnetic field.

Continuous checkpointing of HTM transactions in NVM

This paper addresses the challenges of coupling byte addressable non-volatile memory (NVM) and hardware transaction memory (HTM) in high-performance transaction processing. We first show that HTM transactions can be ordered using existing processor instructions without any hardware changes. In contrast, existing solutions posit changes to HTM mechanisms in the form of special instructions or modified functionality. We exploit the ordering mechanism to design a novel persistence method that decouples HTM concurrency from back-end NVM operations. Failure atomicity is achieved using redo logging coupled with aliasing to guard against mistimed cache evictions. Our algorithm uses efficient lock-free mechanisms with bounded static memory requirements. We evaluated our approach using both micro-benchmarks, and, benchmarks in the STAMP suite, and showed that it compares well with standard (volatile) HTM transactions. We also showed that it yields significant gains in throughput and latency in comparison with persistent transactional locking.

Makalu: fast recoverable allocation of non-volatile memory

Byte addressable non-volatile memory (NVRAM) is likely to supplement, and perhaps eventually replace, DRAM. Applications can then persist data structures directly in memory instead of serializing them and storing them onto a durable block device. However, failures during execution can leave data structures in NVRAM unreachable or corrupt. In this paper, we present Makalu, a system that addresses non-volatile memory management. Makalu offers an integrated allocator and recovery-time garbage collector that maintains internal consistency, avoids NVRAM memory leaks, and is efficient, all in the face of failures. We show that a careful allocator design can support a less restrictive and a much more familiar programming model than existing persistent memory allocators. Our allocator significantly reduces the per allocation persistence overhead by lazily persisting non-essential metadata and by employing a post-failure recovery-time garbage collector. Experimental results show that the resulting online speed and scalability of our allocator are comparable to well-known transient allocators, and significantly better than state-of-the-art persistent allocators.

Energy Aware Persistence: Reducing the Energy Overheads of Persistent Memory

Next generation byte addressable nonvolatile memory (NVM) technologies like PCM are attractive for end-user devices as they offer memory scalability as well as fast persistent storage. In such environments, NVM’s limitations of slow writes and high write energy are magnified for applications that need atomic, consistent, isolated and durable (ACID) updates. This is because, for satisfying correctness (ACI), application state must be frequently flushed from all intermediate buffers, including processor cache, and to support durability (D) guarantees, that state must be logged. This increases NVM access and more importantly results in additional CPU instructions. This paper proposes Energy Aware Persistence (EAP). To develop EAP, we first show that the energy related overheads for maintaining durability are significant. We then propose energy-efficient durability principles that mitigate those costs, an example being flexible logging that switch between performance and energy-efficient modes and a memory management technique that trades capacity for energy. Finally, we propose relaxed durability (ACI-RD) mechanism used under critical low energy conditions that do not affect correctness. The initial results for several realistic applications and benchmark show up to 2x reduction in CPU and NVM energy usage relative to a traditional ACID-based persistence.

Non-volatile main memory management methods based on a file system.

There are upcoming non-volatile (NV) memory technologies that provide byte addressability and high performance. PCM, MRAM, and STT-RAM are such examples. Such NV memory can be used as storage because of its data persistency without power supply while it can be used as main memory because of its high performance that matches up with DRAM. There are a number of researches that investigated its uses for main memory and storage. They were, however, conducted independently. This paper presents the methods that enables the integration of the main memory and file system management for NV memory. Such integration makes NV memory simultaneously utilized as both main memory and storage. The presented methods use a file system as their basis for the NV memory management. We implemented the proposed methods in the Linux kernel, and performed the evaluation on the QEMU system emulator. The evaluation results show that 1) the proposed methods can perform comparably to the existing DRAM memory allocator and significantly better than the page swapping, 2) their performance is affected by the internal data structures of a file system, and 3) the data structures appropriate for traditional hard disk drives do not always work effectively for byte addressable NV memory. We also performed the evaluation of the effects caused by the longer access latency of NV memory by cycle-accurate full-system simulation. The results show that the effect on page allocation cost is limited if the increase of latency is moderate.