Address Translation Research Articles

메모리 주소 변환 공격을 탐지하기 위한 Snoop기반의 커널 검사 시스템

메모리 주소 변환 공격을 탐지하기 위한 Snoop기반의 커널 검사 시스템

Area efficient remote code execution platform with on-demand instruction manager for cloud-connected code executable IoT devices

An energy-area efficient cloud-connected software execution architecture in IoT sensor processor is proposed. A remotely installed sensor device such as an environmental activity monitor is commonly implemented using the conventional embedded processor only providing the fixed services, which includes statically compiled embedded software in on-chip flash memory. Instead of conventional on-chip flash memory for an instruction code area, we adopt an virtually mapped internal memory concept to realize cloud-connected software execution, in where the remote storage area via the IoT platform is indirectly mapped onto the physical address space of the instruction memory using a dynamic address translation technique. The proposed cloud-connected architecture of the system enables on-demand code execution for the instructions, which are fetched from the cloud-side remote storage area in the runtime, instead of using a directly-connected on-chip instruction bus. The proposed storage-less approach may be adopted to reduce the high access current and large chip area overhead by eliminating the on-chip code flash memory. To reduce the access current overhead in order to retrieve the requested instruction, a small-sized RAM scratch pad is adopted for retaining the hot-spot instruction code and early filled with pre-estimated instruction sector. The experimental results show that the proposed technique reduces the energy consumption and packet delay of an IoT device for executing the remote embedded software, as well as the reduced chip area by realizing a storage-less sensor architecture.

TreeFTL: An Efficient Workload-Adaptive Algorithm for RAM Buffer Management of NAND Flash-Based Devices

NAND flash memory is widely used for the secondary storage of computer systems. The flash translation layer (FTL) is the firmware that manages and operates a flash-based storage device. One of the FTL's modules manages the RAM buffer of the flash device. Now this RAM buffer is sufficient to be used for both address mapping and data buffering. As the fastest component of the flash layer interface, effective management of this buffer has a significant impact on the performance of data storage and access. This paper proposes a novel scheme called TreeFTL for this purpose. TreeFTL organizes address translation pages and data storage pages in a tree-like structure in the RAM buffer. The tree enables TreeFTL to adapt to the access behaviors of workloads by dynamically adjusting the partitions for address mapping and data buffering. Furthermore, TreeFTL employs a lightweight mechanism to evict the least-recently-used victim pages when the need arises. Our experiments show that TreeFTL is able to spend 46.6 and 49.0 percent less service time over various workloads than two state-of-the-art algorithms, respectively, for a 64 MB RAM buffer.

Efficient Remote Software Management Method based on Dynamic Address Translation for IoT Software Execution Platform in Wireless Sensor Network

Background/Objectives: In this paper, an efficient remote code execution technique is proposed to implement a storage-less sensor in the Internet-of-Things (IoT) paradigm. Methods/Statistical Analysis: To realize a flexible code update mechanism and to optimize the use of an IoT device in terms of utilizing its various functions, we adopt the concept of remote on-demand code execution (ROCE) to implement a storage-less sensor. Findings: Instead of using a conventional on-chip flash memory for an instruction code, an instruction memory is used wherein the remote storage area based on the IoT platform is virtually mapped onto the address space of the instruction memory using a dynamic address translation technique. The proposed storage-less approach using the remote resource as a virtual code space may be adopted to reduce the high access current and chip area overhead of an on-chip code flash memory. Application/Improvements: The proposed technique reduces the energy consumption and the packet delay of an IoT device for executing the remote embedded software, as well as realizes a storage-less sensor architecture.

Ambitious and Challenging Targets for New Generation Network

Today, the Internet has penetrated almost all the ins and outs of social life, has changed work, communications, social influence and the lifestyle of humankind. However, it is still short of flexibility, transparency etc., due to network address translator overuse, masschanges, uncomfortable protocols, and so on. Hence, more research is necessary into future telecommunications networks based on contemporary networks accompanied by new requisitions and new designs that are compatible with today’s and tomorrow’s demands. This paper researches a new vision of the telecommunication network of the future, its effects on human life and society, and the targets to achieve a new generation network (NwGN). In the paper, we also propose orientation towards an NwGN from the current networks, especially with Vietnam’s telecommunications networks.

IMPLEMENTASI STATIC NAT TERHADAP JARINGAN VLAN MENGGUNAKAN IP DYNAMIC HOST CONFIGURATION PROTOCOL (DHCP)

To build a network interconnect Local Area Network (LAN) that will be needed in the form of Virtual groups Local Area Network (LAN). DHCP IP address given by the router to the PC located in the network. NAT (Network Address Translation) is one method that is used as an IP translation to gain entrance into a different network. NAT (Network Address Translation) can allow a host to go into different networks without allowing the host intended to tap into their networks using VLAN With the two different networks into a single switch can be connected. Giving DHCP IP will allow the network administrator to provide the IP address to a PC for IP assigned automatically by the router. An IP host is forwarded in a network with NAT.

Efficient synonym filtering and scalable delayed translation for hybrid virtual caching

Conventional translation look-aside buffers (TLBs) are required to complete address translation with short latencies, as the address translation is on the critical path of all memory accesses even for L1 cache hits. Such strict TLB latency restrictions limit the TLB capacity, as the latency increase with large TLBs may lower the overall performance even with potential TLB miss reductions. Furthermore, TLBs consume a significant amount of energy as they are accessed for every instruction fetch and data access. To avoid the latency restriction and reduce the energy consumption, virtual caching techniques have been proposed to defer translation to after L1 cache misses. However, an efficient solution for the synonym problem has been a critical issue hindering the wide adoption of virtual caching. Based on the virtual caching concept, this study proposes a hybrid virtual memory architecture extending virtual caching to the entire cache hierarchy, aiming to improve both performance and energy consumption. The hybrid virtual caching uses virtual addresses augmented with address space identifiers (ASID) in the cache hierarchy for common non-synonym addresses. For such non-synonyms, the address translation occurs only after last-level cache (LLC) misses. For uncommon synonym addresses, the addresses are translated to physical addresses with conventional TLBs before L1 cache accesses. To support such hybrid translation, we propose an efficient synonym detection mechanism based on Bloom filters which can identify synonym candidates with few false positives. For large memory applications, delayed translation alone cannot solve the address translation problem, as fixed-granularity delayed TLBs may not scale with the increasing memory requirements. To mitigate the translation scalability problem, this study proposes a delayed many segment translation designed for the hybrid virtual caching. The experimental results show that our approach effectively lowers accesses to the TLBs, leading to significant power savings. In addition, the approach provides performance improvement with scalable delayed translation with variable length segments.

Efficient synonym filtering and scalable delayed translation for hybrid virtual caching

Conventional translation look-aside buffers (TLBs) are required to complete address translation with short latencies, as the address translation is on the critical path of all memory accesses even for L1 cache hits. Such strict TLB latency restrictions limit the TLB capacity, as the latency increase with large TLBs may lower the overall performance even with potential TLB miss reductions. Furthermore, TLBs consume a significant amount of energy as they are accessed for every instruction fetch and data access. To avoid the latency restriction and reduce the energy consumption, virtual caching techniques have been proposed to defer translation to after L1 cache misses. However, an efficient solution for the synonym problem has been a critical issue hindering the wide adoption of virtual caching. Based on the virtual caching concept, this study proposes a hybrid virtual memory architecture extending virtual caching to the entire cache hierarchy, aiming to improve both performance and energy consumption. The hybrid virtual caching uses virtual addresses augmented with address space identifiers (ASID) in the cache hierarchy for common non-synonym addresses. For such non-synonyms, the address translation occurs only after last-level cache (LLC) misses. For uncommon synonym addresses, the addresses are translated to physical addresses with conventional TLBs before L1 cache accesses. To support such hybrid translation, we propose an efficient synonym detection mechanism based on Bloom filters which can identify synonym candidates with few false positives. For large memory applications, delayed translation alone cannot solve the address translation problem, as fixed-granularity delayed TLBs may not scale with the increasing memory requirements. To mitigate the translation scalability problem, this study proposes a delayed many segment translation designed for the hybrid virtual caching. The experimental results show that our approach effectively lowers accesses to the TLBs, leading to significant power savings. In addition, the approach provides performance improvement with scalable delayed translation with variable length segments.

Agile paging

Virtualization provides benefits for many workloads, but the overheads of virtualizing memory are not universally low. The cost comes from managing two levels of address translation---one in the guest virtual machine (VM) and the other in the host virtual machine monitor (VMM)---with either nested or shadow paging. Nested paging directly performs a two-level page walk that makes TLB misses slower than unvirtualized native, but enables fast page tables changes. Alternatively, shadow paging restores native TLB miss speeds, but requires costly VMM intervention on page table updates. This paper proposes agile paging that combines both techniques and exceeds the best of both. A virtualized page walk starts with shadow paging and optionally switches in the same page walk to nested paging where frequent page table updates would cause costly VMM interventions. Agile paging enables most TLB misses to be handled as fast as native while most page table changes avoid VMM intervention. It requires modest changes to hardware (e.g., demark when to switch) and VMM policies (e.g., predict good switching opportunities). We emulate the proposed hardware and prototype the software in Linux with KVM on x86-64. Agile paging performs more than 12% better than the best of the two techniques and comes within 4% of native execution for all workloads.

Hash, Don't Cache (the Page Table)

Radix page tables as implemented in the x86-64 architecture incur a penalty of four memory references for address translation upon each TLB miss. These 4 references become 24 in virtualized setups, accounting for 5%--90% of the runtime and thus motivating chip vendors to incorporate page walk caches (PWCs). Counterintuitively, an ISCA 2010 paper found that radix page tables with PWCs are superior to hashed page tables, yielding up to 5x fewer DRAM accesses per page walk. We challenge this finding and show that it is the result of comparing against a suboptimal hashed implementation---that of the Itanium architecture. We show that, when carefully optimized, hashed page tables in fact outperform existing PWC-aided x86-64 hardware, shortening benchmark runtimes by 1%--27% and 6%--32% in bare-metal and virtualized setups, without resorting to PWCs. We further show that hashed page tables are inherently more scalable than radix designs and are better suited to accommodate the ever increasing memory size; their downside is that they make it more challenging to support such features as superpages.

Performance Analysis of IPv4 to IPv6 Transition Methods

It is an arduous and indolent process to switch to IPv6 technology from the existing IPv4. This paper aims at providing a lucid performance analysis of key techniques used in IPv4 to IPv6 transition. Sustainable and real time topologies are built for each of the three robust techniques, namely, dual stack, tunneling, and network address translation. These implementations are done in an open source Network simulator GNS3 (1.3.13), a wide compatible and realistic simulator. All the topologies are analyzed for latency, efficiency and throughput using wire shark packet analyzer. Networks are built using different commercially used cisco 7200, 3600 and 3700 series routers and used serial and fast ethernet cables for connecting the nodes. All topologies are configured as private, to analyze each technique performance at their maximum potential. This analysis can be found useful in employing the right transition technique depending on the network scenario used as it weigh the advantage and limitation for each technique. The analysis depicts the competence of tunneling for its highest latency comparatively. Among the three methods, Dual Stack displays 100% efficiency in communicating within the network. Network address translation show 94% efficiency as it plays an important role when IPv4 only needs to communicate with IPv6 nodes. In most cases, IPv6 show better performance than IPv4, which lucidly explains the potential of IPv6. The analysis can further be extended to hardware implementation by constructing large topologies and with various other sophisticated routers produced by different vendors.

A unified framework for designing high performance in-memory and hybrid memory file systems

The emerging non-volatile memory technologies provide a new choice for storing persistent data in memory. Therefore, file system structure needs re-studying and re-designing. Our goal is to design a framework that gives high-performance in-memory file accesses and allows a file whose data can be stored across memory and block device. This paper presents a novel unified framework for in-memory and hybrid memory file systems based on the concept that each file has a contiguous Virtual Address Space. Within this framework, the file access for in-memory data can be efficiently handled by address translation hardware and the virtual address space of file. The file accesses for data in block devices are handled by a dedicated page fault handler for file system. A file system called Hybrid Memory File System (HMFS) is implemented based on this framework. Experimental results show that the throughput of HMFS approaches the memory bus bandwidth in best cases. Compared with in-memory file systems, HMFS reaches 5 times, 2.1 times, and 1.6 times faster than EXT4 on Ramdisk, RAMFS, and PMFS, respectively. Compared with EXT4 on SSD and EXT4 using page cache, HMFS also achieves 100 times and tens of times performance improvement, respectively.

Implementation of Network Services on IPV6 Networks

Internet Protocol (IP) layer also known as the network layer is responsible for sending and receiving packets in a network. This task is performed by using a uniquely identified fixed length of addresses known as IP addresses. In the IPv4 protocol, the length of addresses is 32 bits and this gives limit of addresses to 232 = 4,294,967,296. The 32 bit numeric identifier used in the IPv4 was considered enough at the early years of the creation of the internet. Various schemes such as subnetting, Variable Length subnet Mask (VLSM) and the introduction of private IP addresses in combination with Network address Translation (NAT) have been employed to delay the exhaustion of IPv4 as mobile devices increase considerably. With the increase in the world‟s population and the emergence of several mobile devices, it is likely that IPv4 addresses can no longer be enough even with all the interventions introduced. The only viable option is the IPV6. Since the launch of the next generation protocol (IPv6) in June 2012, various studies have been undertaken. Many network administrators, IT professional and even customers wonder what has changed and how difficult or otherwise is it to implement network services on IPv6. This thesis seeks to bring to the fore the various works on implementation of IPv6, and also implement IPv6 networks and use it to investigate the implementation difficulties in the IPv6 connectivity and routing; transition schemes, Quality of Service (QoS), Security and other services such as Content Delivery Networks (CDN); Dynamic Host Configuration Protocol (DHCP); Transmission Control Protocol (TCP) /User Datagram Protocol (UDP); Simple Mail Transport Protocol (SMTP); Hypertext Transfer Protocol (HTTP) and Domain Name System (DNS) and compare their performances with that of IPv4. General Terms Internet Protocol Version 6 (IPv6), Network Services, Transition Techniques

Signaling in IP-Based Networks: Retrospect and Prospect

Protocols have been developed to provide various signaling services in IP-based networks - for example, for quality-of-service (QoS) reservations, or configuring middleboxes such as Network Address Translators (NATs) and firewalls. This article presents a retrospective view on the development of the IETF Next Steps in Signaling protocols, with a more flexible signaling framework than the traditional Resource ReSerVation Protocol (RSVP). The challenges are discussed for signaling in emerging network architectures like software-defined networking, network function virtualization, and service function chaining, as well as ongoing standardization efforts.

Range Translations for Fast Virtual Memory

Modern workloads suffer high execution-time overhead due to page-based virtual memory. The authors introduce range translations that map arbitrary-sized virtual memory ranges to contiguous physical memory pages while retaining the flexibility of paging. A range translation reduces address translation to a range lookup that delivers near zero virtual memory overhead.

COATCheck

Modern computer systems include numerous compute elements, from CPUs to GPUs to accelerators. Harnessing their full potential requires well-defined, properly-implemented memory consistency models (MCMs), and low-level system functionality such as virtual memory and address translation (AT). Unfortunately, it is difficult to specify and implement hardware-OS interactions correctly; in the past, many hardware and OS specification mismatches have resulted in implementation bugs in commercial processors. In an effort to resolve this verification gap, this paper makes the following contributions. First, we present COATCheck, an address translation-aware framework for specifying and statically verifying memory ordering enforcement at the microarchitecture and operating system levels. We develop a domain-specific language for specifying ordering enforcement, for including ordering-related OS events and hardware micro-operations, and for programmatically enumerating happens-before graphs. Using a fast and automated static constraint solver, COATCheck can efficiently analyze interesting and important memory ordering scenarios for modern, high-performance, out-of-order processors. Second, we show that previous work on Virtual Address Memory Consistency (VAMC) does not capture every translation-related ordering scenario of interest, and that some such cases even fall outside the traditional scope of consistency. We therefore introduce the term transistency model to describe the superset of consistency which captures all translation-aware sets of ordering rules.

COATCheck

Modern computer systems include numerous compute elements, from CPUs to GPUs to accelerators. Harnessing their full potential requires well-defined, properly-implemented memory consistency models (MCMs), and low-level system functionality such as virtual memory and address translation (AT). Unfortunately, it is difficult to specify and implement hardware-OS interactions correctly; in the past, many hardware and OS specification mismatches have resulted in implementation bugs in commercial processors. In an effort to resolve this verification gap, this paper makes the following contributions. First, we present COATCheck, an address translation-aware framework for specifying and statically verifying memory ordering enforcement at the microarchitecture and operating system levels. We develop a domain-specific language for specifying ordering enforcement, for including ordering-related OS events and hardware micro-operations, and for programmatically enumerating happens-before graphs. Using a fast and automated static constraint solver, COATCheck can efficiently analyze interesting and important memory ordering scenarios for modern, high-performance, out-of-order processors. Second, we show that previous work on Virtual Address Memory Consistency (VAMC) does not capture every translation-related ordering scenario of interest, and that some such cases even fall outside the traditional scope of consistency. We therefore introduce the term transistency model to describe the superset of consistency which captures all translation-aware sets of ordering rules.

IMPLEMENTASI NETWORK ADDRESS TRANSLATION (NAT) MENGGUNAKAN KERIO CONTROL VERSI 7.4.1 DI PUSAT PENELITIAN BIOTEKNOLOGI – LIPI

Biotechnology Research Center as an institution engaged in the research, the need for data and updated information is an absolute thing. This requirement can be met one of them is the use of information technology either by using the internet. With the increasing number of Internet users in Biotechnology Research Center and order for all users who are members of the Local Area Network (LAN) can utilize the internet needed a good network management. While, during the network management Indonesian Institute of Sciences (LIPI), under the supervision of the Joint Network Team (TGJ – LIPI ) only provide one local IP segment which is limited to only 250 users. While number of internet users in Biotechnology Research Center and more than that number will continue to grow. To overcome these problems, then the LAN network at the Research Center for Biotechnology service facility utilizes Network Address Translation (NAT) contained in Kerio Control software version 7.4.1. The subject of this article is limited to the implementation and configuration of NAT using Kerio Control 7.4.1 version. From these results, we concluded that the implementation of NAT helps all users in the network LAN Biotechnology Research Center get Public IP, so that it can connect to the internet properly.

Protocol Verification of Translation in Mobile Internet Protocol Version 4 and 6

Verifying a protocol means ensuring that it is free of logical errors prior to implementing it. The goal of verifying the protocol is to guarantee that protocol does exactly what the designer intended. This paper presents the methodology to verify protocols in transition phase of Mobile IP. Due to insufficient addresses in IPv4 there is an urgent need to switch to IPv6. Translation is an effective technique that enables IPv4-only devices to communicate with IPv6-only devices. This paper deals with operation of Address translation & Mapping technique in Translation. The Design Analysis in this paper demonstrates methodology to verify translation of IPv4 data packet to IPv6 data packet.

DevCom: Device communities for user-friendly and trustworthy communication, sharing, and collaboration

We present the design, implementation and evaluation of DevCom, a network system that provides users with a trustworthy and user-friendly way to communicate, share and collaborate among distinct groups of devices simultaneously, e.g., home devices, work devices and friends’ devices. DevCom is trustworthy, because reliability, security and privacy issues are automatically taken care of with state-of-the-art cryptography. User-friendliness is ensured through self-configuration, persistent connections in advent of mobility, and by automatically solving problems that network address translation (NAT) and firewalls introduce. An experimental evaluation shows that (1) off-the-shelf applications such as games perform in the same way as they do without DevCom, (2) latency, throughput and processing overhead is low and unnoticeable to users, and (3) persistent connections are automatically supported on devices with changing addresses. A critical analysis from three user perspectives, i.e., a novice, an intermediate user, and an application developer, highlight the user-friendliness of DevCom for a broad range of users.