Address Computation Overhead Research Articles

Minimizing address arithmetic instructions in embedded applications on DSPs

Address arithmetic instructions constitute a big part of the generated code for digital signal processors (DSPs). Most modern digital signal processors (DSPs) provide multiple address registers and a dedicated address generation unit (AGU) which performs address generation in parallel to instruction execution. There is no address computation overhead if the next address is within the auto-modify range. A careful placement of variables in memory is utilized to reduce the number of address arithmetic instructions and thus generate compact and efficient code. The simple offset assignment (SOA) problem concerns the layout of variables for machines with one address register and the general offset assignment (GOA) deals with multiple address registers. Both these problems assume that each variable needs to be allocated for the entire duration of a program. Both SOA and GOA are NP-complete. In this article, we present effective solutions using simulated annealing (SA) for the simple and the general offset assignment problems with variable coalescing where two or more non-interfering variables can be mapped into the same memory location. Results on several benchmarks show the significant improvement from our proposed techniques compared to other heuristics in the literature.

Storage Optimization through Offset Assignment with Variable Coalescing

Most modern digital signal processors (DSPs) provide multiple address registers and a dedicated address generation unit (AGU) which performs address generation in parallel to instruction execution. There is no address computation overhead if the next address is within the auto-modify range. A careful placement of variables in memory is utilized to decrease the number of address arithmetic instructions and thus to generate compact and efficient code. The simple offset assignment (SOA) problem concerns the layout of variables for machines with one address register and the general offset assignment (GOA) deals with multiple address registers. Both these problems assume that each variable needs to be allocated for the entire duration of a program. Both SOA and GOA are NP-complete. In this article, we present effective heuristics for the simple and the general offset assignment problems with variable coalescing where two or more non-interfering variables can be mapped into the same memory location. Results on several benchmarks show the significant improvement of our proposed heuristics compared to other heuristics in the literature.

CODE SIZE REDUCTION FOR ARRAY INTENSIVE APPLICATIONS ON DIGITAL SIGNAL PROCESSORS

Optimizing the code size for applications that run on a digital signal processors (DSPs) is a crucial step in generating high-quality and efficient code. Most modern DSP provide multiple address registers and dedicated address generation units that provide address generation in parallel to instruction execution. There is no address computation overhead if the next address is within the auto-modify range of the address register. Many DSP algorithms have an iterative pattern of references to array elements within loops. Thus, a careful assignment of array references to address registers (called the address register allocation or ARA problem) reduces the number of explicit address arithmetic instructions as well as the execution cycles. In this paper, we present an optimal integer linear programming formulation for the address register allocation problem which incorporates code restructuring techniques. In addition, we have developed a Genetic Algorithm solution for the ARA problem that allows us to get near-optimal solutions in a reasonable amount of time for large embedded applications. Results on several benchmarks show the effectiveness of our techniques compared to other techniques in the literature.

Evaluating address register assignment and offset assignment algorithms

In digital signal processors (DSPs), variables are accessed using k address registers. The problem of finding a memory layout, for a set of variables, that minimizes the address-computation overhead is known as the General Offset Assignment (GOA) problem. The most common approach to this problem is to partition the set of variables into k partitions and to assign each partition to an address register. Thus, effectively decomposing the GOA problem into several Simple Offset Assignment (SOA) problems. Many heuristic-based algorithms are proposed in the literature to approximate solutions to both the variable partitioning and the SOA problems. However, the address-computation overhead of the resulting memory layouts are not accurately evaluated. This article presents an evaluation of memory layouts that uses Gebotys' optimal address-code generation technique. The use of this evaluation method leads to a new optimization problem: the Memory Layout Permutation (MLP) problem. We then use Gebotys' technique and an exhaustive solution to the MLP problem to evaluate heuristic-based offset-assignment algorithms. The memory layouts produced by each algorithm are compared against each other and against the optimal layouts. The results show that even in small access sequences with 12 variables or less, current heuristics may produce memory layouts with address-computation overheads up to two times higher than the overhead of an optimal layout.

Gather/scatter hardware support for accelerating Fast Fourier Transform

As we enter the multi-core era, seeking methods to boost the performance of single-threaded applications remains critical. Achieving gains in processor performance by increasing the operating frequency has begun to meet more obstacles. However, significant performance improvements can be achieved by extending the capability of the processor with the addition of hardware support, which makes much more effective use of the available transistors. This paper presents a novel hardware support called, DistTree, to speed up processor performance. The DistTree hardware automates gather and scatter operations for applications with complex but predictable memory access patterns like the Fast Fourier Transform (FFT). With this hardware support integrated with a modern microprocessor (the Alpha architecture in our experiments), the FFT performance can reap a more than twofold increase when compared against the FFTW library, a state-of-the-art implementation. The DistTree hardware support enables the processor to spend the majority of processor cycles on executing the computations of an algorithm by reducing both the arithmetic and address computation overhead. Therefore, the performance of many single-threaded applications can be significantly increased.

Minimization of Data Address Computation Overhead in DSP Programs

Modern digital signal processors (DSPs) provide dedicated address generation units (AGUs) which support data memory access by indirect addressing with automatic address modification in parallel to other machine operations. There is no address computation overhead if the next address is within the auto-modify range. Typically, optimization of data memory layout and address register assignment allows to reduce both execution time and code size of DSP programs. In this paper, we present an optimization technique for integrated data memory layout generation and address register assignment. We use a generic AGU model which captures important addressing capabilities of DSPs such as linear addressing, modulo addressing, auto-modifying, and indexing within a given auto-modify range. Experimental results demonstrate that the proposed technique significantly outperforms existing optimization strategies.