Additional Parasitic Capacitance Research Articles

Analysis of self-heating-related instability in n-channel low-temperature polysilicon TFTs with different S/D contact hole densities

This study examines self-heating-related instability in n-channel low-temperature polysilicon thin-film transistors with different source/drain contact hole densities. Devices with more contact holes exhibit a higher on-current without additional parasitic capacitance, further enhancing the RC delay property. For high-current-induced self-heating stress, a device with one contact hole has one hump due to the kink effect. However, a device with six contact holes has two humps, induced by the kink effect and thermionic field emission. COMSOL simulations of heat distribution and energy bands are performed to examine the different degradation behaviors, and then physical models are proposed.

Analysis of strong-arm comparator with auxiliary pair for offset calibration

This paper analyzes the principle of the input-referred off calibration using the auxiliary pair for Strong-Arm comparator as well as its impact from the additional common-mode current and parasitic capacitance on the input-referred noise, offset, and decision time in detail. The comparison with the simulation results demonstrates the accurate prediction with the proposed analysis. This paper also discusses the design guideline to optimize the Strong-Arm comparator with the auxiliary pair for offset calibration.

Parameter Identification of One-Diode Dynamic Equivalent Circuit Model for Photovoltaic Panel

An equivalent electric circuit is exploited for interpreting the dynamic behavior of a photovoltaic (PV) panel based on the commonly used one-diode model with an additional parasitic capacitance. By drawing rippled currents from the PV panel with a boost converter, the circuit parameters of the model can be obtained simply from a few test points without the need of the intrinsic parameters of the PV panel given by datasheets. Experimental tests are carried out on a laboratory system to demonstrate the capability of simulating the dynamic responses of a PV panel with the derived circuit parameters.

CM Conducted EMI mitigation in flyback PFC converter

The switched mode power supplies offer many advantages in power conversion. But they offer low power factor and generate electromagnetic interference (EMI). The low power factor can be improved by a front-end power factor correction (PFC) unit. However, they also generate EMI in both differential mode and common mode (CM). The interwinding capacitance of the transformer and parasitic capacitance between the heat sink and ground are major contributors to CM noise. The traditional method to minimize the CM noise by using a line filter consists of CM choke and Y capacitor. But, CM noise causes leakage current to flow to the ground through the Y capacitor. This leakage current has to be restricted as per the standards for commercially used equipment and medical instruments. The technique proposed here reduces the values of Y capacitor thereby reducing the leakage current. This can be reduced by minimizing the predominant parasitic capacitances of the HF transformer used in the PFC converter. This paper presents a technique for reducing these parasitic capacitances by incorporating an additional parasitic capacitance noise cancellation winding (PCW). A flyback transformer winding capacitance model depicting the parasitic capacitances is considered, and a novel method to determine this parasitic capacitance is presented. Using this model, the CM Conducted EMI in a flyback PFC is determined by simulation and experimentation. These simulation and experimentation results are used to design an EMI line filter to reduce the Conducted CM noise to complaint levels. The value of Y capacitor now is reduced due to the addition of PCW thereby reducing the size and cost of the filter. This technique has been validated experimentally on a 30-W power factor correction flyback converter working in critical conduction mode.

Improvement of p-type GaAs0.51Sb0.49 metal-oxide-semiconductor interface properties by using ultrathin In0.53Ga0.47As interfacial layers

The effects of interfacial In0.53Ga0.47As layers on Al2O3/GaAs0.51Sb0.49 metal-oxide-semiconductor (MOS) structures on InP substrates have systematically been studied. It is found that the interfacial InGaAs layers can reduce Dit values of the Al2O3/GaAsSb MOS interfaces down to 3–4 × 1011 cm−2 eV−1, which is almost one order of the magnitude lower than in the MOS interfaces without any InGaAs interfacial layers. It is also found that the InGaAs thickness of 1.0–1.5 nm is sufficient to reduce Dit to this low value. In order to obtain these results, the influence of an additional parasitic conductance and capacitance related to the GaAsSb/InP heterointerface needs to be considered, because the C-V characteristics of Al2O3/GaAs0.51Sb0.49/InP MOS capacitors in the accumulation region exhibit strong frequency dispersion, regardless of the InGaAs interfacial layer. We present through simulation of the C-V characteristics using a 2-dimensional device simulator that the correction of this series resistance and capacitance by using an equivalent circuit model can effectively eliminate the influence of the potential barrier at the GaAsSb/InP heterointerface from the experimental C-V ones, allowing us to employ the conventional conductance method for extracting interface trap density (Dit).

Record combination fmax · Vbr of 25 THz·V in AlGaN/GaN HEMT with plasma treatment

A combination of high maximum oscillation frequency (fmax) and breakdown voltage (Vbr) was achieved in AlGaN/GaN high electron mobility transistors (HEMTs) with N2O plasma treatment on the access region. The breakdown voltage is improved from 37 V to 80 V due to the formation of oxide layer in the gate region. A suppressed current collapse is obtained due to plasma treatment on the gate-source and the gate-drain regions. The effect of the present passivation method is almost the same with that of the conventional SiN passivation method, meanwhile it can avoid introducing additional parasitic capacitance due to thinner thickness. The small signal measurement shows that HEMT can yield fT and fmax of 98 and 322 GHz, respectively, higher than that of 70 and 224 GHz for the non-treated HEMT. By using the plasma treatment technique, the HEMT can simultaneously exhibit high fmax and Vbr with a record fmax⋅Vbr of 25 THz⋅V.

Resistive nickel temperature sensor integrated into short-gate length AlGaN/GaN HEMT dedicated to RF applications

This letter describes a new method to extract the operating temperature in short-gate length AlGaN/GaN high electron mobility transistors (HEMTs) dedicated to RF applications. For this goal, a nickel resistive sensor is integrated into the HEMT active area close to the hot thermal spot thanks to a well-suited technological process. Operating temperature of the HEMT is extracted showing the capabilities of this method to monitor the thermal behavior of the device. Furthermore, it is shown that dc and RF characteristics are not degraded by additional parasitic capacitance and/or sensor biasing.

(Keynote) FDSOI Past, Present and Future

FDSOI is quickly becoming a technology offering that can deliver next generation performance with superior low power operation at a significant cost advantage. Researchers have actively pursued alternatives to conventional bulk and PDSOI transistors for well over 10 years. However, there was not enough compelling need to change until conventional CMOS scaling dramatically slowed. Beyond the 28nm node new device architectures were needed to continue the scaling trend. FDSOI was always thought to be an attractive option since of all the alternative approaches it is the most similar to conventional bulk or PDSOI. This is mainly due to the fact that it is planar and thus much of the process and design methodology can be re used from previous nodes. On the other hand several key issues for FDSOI were known and thought to be fundamental challenges. Specifically silicon consumption, high external resistance and parasitic capacitance were identified as major hurdles. FDSOI relies upon the thin channel to control short channel effects. For example a channel thickness of approximately 6nm is required to maintain good electrostatics for a transistor with Lg=20nm. Maintaining thin silicon in the channel while still preserving silicon in the source-drain regions is a big process challenge. We have carefully optimized several key process steps including the spacer etch process to eliminate excessive silicon consumption. As shown in Fig. 1 the zero loss spacer process features a partial etch using reactive ion etching. In order to minimize silicon consumption, the spacer etch is terminated before the spacer material is completely removed from the horizontal surfaces and the dry etch cannot consume silicon. The residual spacer material is removed as part of the pre epi clean for raised source-drain. Since the wet etch for the pre-clean is highly selective to the silicon, there is no silicon consumption. High external resistance was thought to be a significant challenge for FDSOI mainly in part due to the silicon consumption from the spacer process but also from the junction formation process. Ion implantation is well known to cause damage in thin silicon even with high temperature activation anneal. The silicon damage caused by the ion implantation can also cause defective epitaxial growth during the raised source drain process. We have solved the challenge of junction formation for FDSOI by developing an implant last scheme. After the spacer module is completed the raised-source and drain is formed. Since the ion implant is done into the thick raised-source drain, the damage created is healed during the activation anneal. Parasitic capacitance is another known issue for devices with raised-source drain. We have developed a facetted epi process which eliminates a significant component of the additional parasitic capacitance caused by the raised-source drain (Fig. 2). 1 We have also developed several key elements that enable high performance FDSOI circuits. In-situ doped SiGeB for raised source-drain has been developed to reduce contact resistance and form abrupt junctions for pFETs. SiGe channel is another innovation we have developed to enable high performance by increasing hole mobility. Fig. 3 shows the benefit of the strained SiGe raised source-drain and the SiGe channel.2 FDSOI is scalable and can be used for several technology nodes. Gate length scaling for FDSOI can be accomplished by thinning the silicon. Reverse back bias can also be used to improve short channel effects and enable scaling. Figure 4 shows the improvement in short channel control as the silicon is thinned down to 3.5nm Remarkably the external resistance of the devices is not compromised as evidenced by the Ion vs Ioff comparison to devices with 6nm channel thickness. The same figure also shows the improvement in electrostatic behavior with reverse back bias.3 Additional improvements in FDSOI performance can be achieved by strained silicon on insulator technology. Figure 5 shows the benefit of the strained silicon channel for nFETs.4 Table 1 shows a comparison of state of the art FDSOI research transistors to FinFETs.5It is interesting to note that the FDSOI devices can achieve competitive drive currents at dramatically shorter gate-lengths thereby improving circuit performance. It is also interesting to note the FinFETs are normalized to the footprint which is 30% greater than the effective channel width. References K. Cheng et. al. IEDM 2010.K. Cheng et. al. IEDM 2013.A. Khakifirooz et. al. EDL 2012.A. Khakifirooz et. al. VLSI 2012.Q. Liu et. al. IEDM 2014. Figure 1

Effect of Bulk-Accumulation on Switching Speed of Dual-Gate a-IGZO TFT-Based Circuits

The effect of bulk accumulation on switching speed of dual-gate amorphous indium–gallium–zinc-oxide thin-film transistor (TFT)-based circuits is investigated. Given that bulk accumulation is achieved by synchronized driving of the top gate (TG) and bottom gate, it can be modulated by varying the length of the TG ( $\textrm {L}_{{{\textrm {TG}}}}$ ) for fixed source–drain distance ( $L$ ). It is confirmed from fabricated ring oscillators that switching speed increases with increasing $\textrm {L}_{{{\textrm {TG}}}}$ for fixed $L$ , verifying that bulk accumulation improves switching speed. However, switching speed drops dramatically when the TG overlaps the source/drain electrodes due to additional parasitic capacitance. TFT-circuits with the longest, but nonoverlapping TGs are demonstrated to exhibit the fastest switching speed; operation frequency exceeding 2.63 MHz for input voltage $\textrm {V}_{{{\textrm {DD}}}}$ of 20 V, which is also the fastest among all inverted staggered amorphous-oxide-semiconductor TFT-based circuits.

Removal of Negative-Bias-Illumination-Stress Instability in Amorphous-InGaZnO Thin-Film Transistors by Top-Gate Offset Structure

A highly stable, dual-gate (DG) amorphous, indium-gallium-zinc oxide (a-IGZO) thin-film transistor (TFT) with an offset top-gate (TG) is reported. Given that both gates are opaque and electrically tied together, the TG functions as a lightshield and drain-current (IDS) enhancer as synchronized gate-voltage (VGS) sweep induces bulk-accumulation (BA) at positive voltages. It is demonstrated here that regardless of the offsets between the TG and source/drain electrode, this BA a-IGZO TFT is immune to negative bias and light-illumination stress (NBIS) when the TG covers at least 50% of the channel region. Therefore, high performance BA a-IGZO TFTs that are also immune to NBIS can be designed without introducing additional parasitic capacitance that occurs when the TG overlaps the source and/or drain electrode(s).

The Wheeler Method for the Measurement of the Efficiency of Differentially-Driven Microstrip Antennas

This communication reports the application of the Wheeler method for the measurement of the efficiency of differentially-driven microstrip antennas. The S-parameter method and the mixed-mode S-parameter method are both used to obtain the differential impedance with and without the cap. It is shown that although additional parasitic inductance and capacitance are introduced from the dual feeds, the parallel RLC model is the valid model to use for the measured probe-fed differentially-driven microstrip antennas.

Characteristics of Two-Stage Γ-Gate on AlGaAs/InGaAs/AlGaAs DH-HEMTs by Using AlGaAs/InGaP Etching-Stop Layers

Al0.22Ga0.78As/In0.18Ga0.82As/Al0.22Ga0.78As double heterojunction high electron mobility transistors (DH-HEMTs) with gate structures of traditional planar gate (PG), one-stage gamma-gate (1SΓG) and two-stage gamma-gate (2SΓG) formed by using the Al0.22Ga0.78As/In0.49Ga0.51P etch-stop layers (ESL) are simulated and presented in this work. Based on this proposed ESL structure design, the fabrication and implementation of studied DH-HEMT device with 1SΓG and 2SΓG could be expected. Both ΓG-structure devices show the better electric field property compared to PG-device. Simulated results reveal that there are no significant differences in common-source voltage-current characteristics among all studied devices. The obtained drain current density and transconductance of all studied devices are about 220 mAmm-1and 265 mSmm-1. However, the current stability of ΓG-devices with larger bias operation would be improved due to its edge-effect of ΓG extended-region. In addition, the electric field intensity under the gate-footprint is effectively reduced by both studied ΓG structures. The electric field peak value of PG-device is 498 kV cm-1, and it would be reduced down to about 210 kVcm-1and 178 kVcm-1for 1SΓG- and 2SΓG-device, respectively. On the other hand, some frequency property dropping is observed from studied device with 1SΓG or 2SΓG due to the side-edge extension of ΓG-device would create the additional parasitic capacitance. The obtained cut-off frequencies are 15 GHz, 10.5 GHz and 10 GHz for PG-, 1SΓG- and 2SΓG-device (at VGS=+5 V and VGS=-0.75 V), respectively.

Comparison of passivation layers for AlGaN/GaN high electron mobility transistors

AlGaN/GaN high electron mobility transistors require surface passivation layers to reduce the effects of surface traps between the gate and drain contacts. These traps lead to the creation of a virtual gate and the associated collapse of drain current under rf conditions. The authors have investigated three different materials for passivation layers, namely thin (7.5 nm) Al2O3 and HfO2 deposited with an atomic layer deposition system and conventional, thick (200 nm) plasma enhanced chemically vapor deposited SiNX. The latter is found to be the most effective in reducing drain current loss during gate lag measurements in both single and double pulse mode, but also reduces fT and fMAX through additional parasitic capacitance.

Stacked Spiral Inductor Design and Modeling for Fully-Integrated DC-DC Converters

A structure of multi-layer spiral inductor having parallel and series branches of the metal strip was designed for fully-integrated DC-DC converters. As the result that the parallel branching structure greatly reduced the series resistance and the series branching structure greatly improved the series inductance of the inductor, the structure can achieve quality factor and current capability enhancement while compatible with conventional CMOS process. The quality factor was quantitatively analyzed with a scalable model and its origin was investigated at a structural point of view. From the experiment results, the substrate effects can be neglected in the interesting frequency range, 50MHz -500MHz, and the quality factor is enhanced beyond the additional parasitic capacitance.

A Novel Spacer Process for Sub-10-nm-Thick Vertical MOS and Its Integration With Planar MOS Device

We demonstrate vertical capacitors using a novel spacer process capable of fin thickness down to 5 nm. We also integrate this process compatibly with planar devices on the same die using minimal additional mask steps. Various implant conditions, order of implant step, and starting substrate dopings are studied and best conditions identified through TSUPREM4 simulations and later through experiments to ensure process robustness and dopant tunability for the vertical devices as well as to ensure comparable performance for planar and vertical devices. In anticipation of usage of this process in a high-density environment, the impact of isolation density on the leakage characteristics of vertical capacitors is also studied. After simultaneously fabricating planar and vertical structures, electrical characterization using capacitance-voltage (C-V) and current-voltage (I-V) measurements is performed. Functional capacitors for both types of devices are obtained. Oxide thickness is backtracked using I-V, C-V, and TEM and yield consistent results. The leakage current shows expected trends with voltage and is successfully fitted using prevalent tunneling models. The vertical structures are found to suffer from two problems: a larger leakage current and an additional planar parasitic capacitance due to a finite polysilicon gate thickness. The larger leakage is attributed to thin corners as confirmed by higher leakage in structures having a larger fraction of corner area (higher isolation density structures). A modified novel vertical device process circumventing both these problems by yielding thicker bottom and corner oxides is proposed and experimentally demonstrated. Finally, a path to extending this process for vertical transistor fabrication is shown in simulations

Analysis on the effect of parallel current path on the quality factor of CMOS spiral inductors for 1–10 GHz

A structure of spiral inductor having a parallel current path through the branch of the metal strip was designed to achieve a quality ( Q) factor enhancement compatible with conventional CMOS and/or established SiGe process in RF and microwave arena. The Q factor enhanced by 12% was quantitatively analyzed with a lumped-element model and its origin was investigated at a structural point of view. As a result we noted that the parallel-branching structure greatly reduced the series resistance of the inductor at a high frequency range of GHz by suppressing current crowding and in turn enhanced the Q factor beyond the additional parasitic capacitance.

Sawyer–Tower hysteresis measurements on micron sized Pb(Zr,Ti)O3 capacitors

We have performed Sawyer–Tower hysteresis measurements on micron sized Pb(Zr,Ti)O3 (PZT) capacitors prepared on Pt/Ti/SiO2/Si substrates and patterned with a focused ion beam. Owing to a numerical compensating technique, we show that the increase of both linear dielectric constant εr and maximum polarization Pmax, when decreasing the size of the capacitors, is artificial and mainly due to the parasitic effect of the probing setup. Moreover, a suitable method is proposed to accurately determine and correct for the additional parasitic capacitance in parallel with the standard capacitor. Under these conditions, the dielectric and ferroelectric properties of micron sized PZT capacitors are found to be quite similar to those measured on a large contact, i.e., the device properties are area independent.