Adaptive Frequency-locked Loop Research Articles

A 2.4-GHz Sub-Sampling PLL With an Adaptive and No Power Contribution FLL Achieving 103.58 fs rms Jitter and −257.8 dB FOM

A sub-sampling PLL (SSPLL) employing an adaptive frequency-locked loop (FLL) without static power consumption is proposed in this letter. A new unlock detection mechanism and a configurable PFD are realized in the adaptive FLL. With the new unlock detection mechanism, while the FLL that contains phase detector, divider, and charge pump dissipates no power during the locked steady state, it automatically starts when external interferences disturb the locked state. The optimized dead zone in the configurable PFD ensures a rapid relocking operation. Based on the proposed adaptive FLL, the 2.4 GHz SSPLL is fabricated in a 40-nm CMOS process. It achieves −128.5 dBc/Hz at 1 MHz offset frequency and the rms jitter is 103.58 fs integrated from 10 k to 10 MHz. It consumes 1.55 mW at 1 V supply and achieves −257.8 dB FOM.

An Enhanced Adaptive Frequency-Locked Loop Based on Fixed-Length Transfer Delay

The fixed-length transfer delay-based adaptive frequency-locked loop (TD-AFLL) has drawn much attention due to its concise structure and faster response speed than conventional second-order generalized integrator-based FLL. However, the application of TD-AFLL is still limited owing to the poor performance in terms of phase-angle/amplitude detection under distorted grid conditions. This paper explores an inherent input-output relationship of TD-AFLL, and a notch filter is employed to represent its filtering feature. Then a high-order filter is designed based on this notch filter, and an enhanced TD-AFLL (ETD-AFLL) with improved phase-angle/amplitude detection is further derived. The ETD-AFLL highly improves the phase-angle/amplitude detection accuracy under distorted grid conditions yet keeps the same fast response speed as TD-AFLL. In addition, the ETD-AFLL only requires a slightly additional computational cost. Experimental results are given to support the proposed ETD-AFLL.

A prefilter to improve the performance of transfer delay-based synchronization technique under distorted grid conditions

The transfer delay-based adaptive frequency-locked loop (TD-AFLL) is a recently proposed synchronization technique. It has fast respond speed in ideal grid, but the performance degrades significantly in distorted grid. In this paper, a prefilter is proposed to enhance the robustness and harmonic rejection of the TD-AFLL. A fixed-coefficient bandpass filter (FCBF) is selected as the prefilter, which benefits from a simple structure and avoids the influence of frequency feedback dynamic of the TD-AFLL. Compare with standard TD-AFLL, the proposed FLL exhibits stronger harmonic rejection capability. Experimental results verify the effectiveness and advantages of the proposed technique.

A Fixed-Length Transfer Delay Based Adaptive Frequency-Locked Loop for Single-Phase Systems

This letter presents an adaptive frequency-locked loop (FLL) with fixed-length transfer delay units for single-phase systems. By analyzing the relationship between the grid voltage and its transfer delay signals, a linear regression model of the grid voltage is established. Accordingly, a transfer delay based adaptive FLL (TD-AFLL) is proposed. A mathematic proof indicates that the proposed TD-AFLL can reject both phase offset errors and double-frequency oscillatory errors. Thus, the grid voltage parameters can be estimated accurately, even when the frequency drifts away from its nominal value. Moreover, fast dynamics of the TD-AFLL are achieved due to the transfer delay structure. Experiments verify the effectiveness of the proposed method.

Turbocharger Rotational Speed Estimation via Acoustic Measurements

Abstract This paper deals with the estimation of the turbocharger rotating speed via the numerical processing of the overall sound emissions acquired via a microphone placed under the vehicle hood. As a matter of fact, this kind of signals represents an extremely rich information source about the operating conditions of all the noisy powertrain subsystems. The core of the scheme is represented by an adaptive Frequency Locked-Loop (FLL) filter that is properly designed so as to extract useful frequency content from the acquired audio signals. The whole architecture, requiring the use of a single microphone only, can be considered innovative and low-cost for automotive applications. Experimental outcomes demonstrate that the approach is ready to be introduced in the Engine Control Unit (ECU) in order to implement suitable strategies for turbocharger control.

Generalized GNSS Signal Carrier Tracking—Part II: Optimization and Implementation

This paper presents the performance analysis and the optimizations of the generalized phase locked loop (PLL) and the generalized frequency locked loop (FLL). Using the minimum mean square error (MMSE) criterion as a performance measure, the optimal solutions for the generalized PLL and FLL designs under various scenarios: strong and weak signal strength, low and high dynamic, and good and poor oscillator quality are investigated. An adaptive PLL based on automatically adjustment of the integration time and loop parameters in an optimized manner is proposed. An adaptive FLL that operates with the optimal loop parameters is also presented. Simulation results demonstrate the effectiveness of the proposed generalized closed-loop tracking architecture and validate the proposed adaptive tracking schemes.

Synchronization optimization method of adaptive frequency-locked loop without DC component interference

Synchronization optimization method of adaptive frequency-locked loop without DC component interference

Time synchronization over the Internet using an adaptive frequency-locked loop

This paper describes the operation of an algorithm for synchronizing the time of computers using messages transmitted over packet-switched networks such as the Internet. The algorithm configures itself to realize any specified performance level at minimum cost (measured in computer cycles or network bandwidth). If the highest possible accuracy is requested, the performance will be limited by the larger of the instability of the local clock oscillator or the noise in the measurement process between the client and the server; uncertainties of about 8 ms RMS have been obtained using standard workstations and average network connections. Lower accuracy can be realized at substantially lower cost because the cost varies approximately as the inverse of the accuracy squared over a wide range of these parameters. The algorithm makes better use of scarce network bandwidth than previous methods. This improvement is realized by using a pure frequency-locked loop (rather than mixed frequency/phase locking algorithms currently proposed for the NTP) with unequal spacing between calibration cycles. The result is a cleaner separation between network noise and clock noise, which is especially important when the highest possible accuracy is desired. In addition, the algorithm is an improvement over the pure-FLL "Interlock" algorithm described previously because it is self configuring. In addition to supporting an explicit trade-off between cost and accuracy, the algorithm provides better performance than previous methods because it is better able to adapt itself to fluctuations in the asymmetry of the network delay.