Adaptive Continuous-time Linear Equalizer Research Articles

A 25-Gb/s dual-loop adaptive continuous-time linear equalizer based on power comparison for the optical transmitter

A new dual-loop adaptive continuous-time linear equalizer (CTLE) based on power comparison is proposed to realize a 25-Gb/s optical transmitter. The adaptive CTLE controls the high-frequency gain peaking of the loop regulation path to match the configuration of the boost factor for improved adaptive capacity and power comparison accuracy. A digital control method is used to operate two power comparison loops with different running cycles for increased power comparison accuracy and reduced power consumption of the adaptive control process. Measurements of an adaptive CTLE fabricated by the 0.18 μm SiGe BiCMOS process showed that it was able to compensate for the coaxial cables with an attenuation of at least −11.4 dB @12.5 GHz. The adaptive CTLE only consumed 22.8 mW from a 1.8-V power supply, resulting in energy efficiency at 0.91 pJ/b.

A 5-Gb/s Adaptive Continuous Time Linear Equalizer Using Ferroelectric Capacitor

This article presents a 5-Gb/s continuous-time linear equalizer (CTLE) for serial link interface where adaptive nature is achieved using a ferroelectric capacitor. This barium strontium titanate (BST)-based STPTIC-15G2 capacitor model from STMicroelectronics provides a smooth 5:1 tuning range for a voltage range of 0&#x2013;18 V and eliminates the use of blocking capacitor required in case of varactor diode. The tunability of the high-pass filter response of the proposed CTLE provides the flexibility to meet the allocated loss budget of any serial link more precisely than a design with a discrete value capacitor. Also, its design methodology is much simpler than conventional MOSFET-based CTLE. Moreover, it avoids the use of complex algorithms seen in the case of digital equalization. For validation, the design is implemented on an FR4 board. While studying the data rate tolerance and channel tolerance of the printed prototype, the measured results closely match the simulation results. The compensation level of the equalizer is verified for an FR4 channel by varying its length from <inline-formula> <tex-math notation="LaTeX">$7^{\prime \prime }$ </tex-math></inline-formula> to <inline-formula> <tex-math notation="LaTeX">$28^{\prime \prime }$ </tex-math></inline-formula> which is equivalent to a change in insertion loss from 1.3 to 5.2 dB at 2.5 GHz, which is the Nyquist frequency for a 5-Gb/s signal. Also, for a <inline-formula> <tex-math notation="LaTeX">$28^{\prime \prime }$ </tex-math></inline-formula> FR4 channel, a channel loss requirement of 8&#x2013;9.5 dB is achievable by simply varying the applied bias to the ferroelectric capacitor from 0 to 10 V.

A 28-nm CMOS 11.2-Gbps Receiver based on Adaptive CTLE and Adaptive 3-Tap DFE With Hysteresis Low-pass Filter

This paper proposes a receiver design incorporating both an adaptive continuous-time linear equalizer (CTLE) and an adaptive decision-feedback equalizer (DFE). The CTLE utilizes a merged rectifier and error amplifier, improving the DC gain and reducing the current consumption. Offset cancelation of the CTLE is performed by adaptively adjusting the load resistance of a CTLE cell. The DFE adopts the technique of using a slave latch behind a current summer for the relaxed timing constraint but excludes other auxiliary circuits that perform a master-latch function. The proposed low-pass filter with a hysteresis can suppress the oscillation of the DFE tap coefficients and the data level in the steady state. Fabricated in 28-nm CMOS process, the prototype receiver shows that the measured BER is less than 10<SUP>-14</SUP> at 10.4 Gb/s for an 18-inch FR4 trace and at 11.2 Gb/s for a 12-inch FR4 trace, respectively, with both the adaptive CTLE and the adaptive DFE activated. Operating at 11.2 Gb/s, the energy efficiency of the receiver is 5.36 pJ/bit.

Innovative 28 Gb/s quarter rate receiver with data-rate-tolerant adaptive continuous-time linear equalizer

This paper presents a 28 Gb/s receiver with a data-rate-tolerant adaptive continuous-time linear equalizer (CTLE). The adaptive CTLE works based on the spectrum balancing method. An equalizer boost control loop is used to adjust the equalizer boost while a corner frequency control loop guarantees data-rate adaption. The speed of similar devices is limited by the necessary slicer. In this study, rather than the output signal of a slicer, the recovered data is used as the input for the corner frequency control loop. A data sampler may have oversize bandwidth during the sample period and a high gain during the regeneration period, thus the proposed structure can secure a clean waveform at high speeds. The quarter rate structure further relaxes the slicer-related speed limit. The receiver consumes 232.2 mW with a 1.2 V supply when realized in 55-nm CMOS technology while the equalizer consumes 70 mW.

A 0.1-pJ/b/dB 1.62-to-10.8-Gb/s Video Interface Receiver With Jointly Adaptive CTLE and DFE Using Biased Data-Level Reference

In this article, a 1.62-to-10.8-Gb/s video interface receiver with jointly adaptive equalization is presented. Sign–sign least-mean-squares (SSLMS) algorithm is applied to adaptation for not only a decision feedback equalizer (DFE) but also a continuous-time linear equalizer (CTLE) to unify the adaptation methods. This approach facilitates concurrent adaptation that results in short adaptation time and also reduces the extra hardware and power consumption. An average value of fourth- and fifth-post-cursors is used as an indicator for CTLE adaptation, and the validity is substantiated by numerical analysis and simulation. Furthermore, the concept of a biased data-level reference (dLev) is proposed and analyzed to alleviate insufficient adaptation of the SSLMS algorithm in the presence of pre-cursor inter-symbol interference (ISI). The proposed dLev is acquired by simply adjusting up and down ratios of the dLev update equation. The prototype test chip is implemented in 65-nm CMOS technology and occupies an active area of 0.174 mm2. The proposed adaptive equalizers compensate for the channel loss of up to 34 dB at 10.8 Gb/s. Total power consumption of the receiver is 37.2 mW at 10.8 Gb/s, and the figure of merit (energy efficiency per channel loss at Nyquist frequency) of 0.1 pJ/b/dB is achieved.

A 36 Gb/s wireline receiver with adaptive CTLE and 1-tap speculative DFE in 0.13 µm BiCMOS technology

This paper presents a 36 Gb/s receiver equalizer including an adaptive continuous time linear equalizer (CTLE), which is based on slope detection and a half-rate speculative decision feedback equalizer (DFE) in 0.13 µm BiCMOS technology for high speed serial link. The CTLE with middle frequency compensation can not only adjust the ratio of high frequency and low frequency components adaptively, but also provide a small amount of equalization to middle frequency range. A half-rate speculative DFE, which is connected to the back of the CTLE, can satisfy the time constraints and eliminate the residual inter-symbol interference. The chip area including pads is about 1.2 mm2 and the power consumption is about 750 mW under 3.3 V power supply. Measurement results show that the receiver chip can effectively equalize 24 dB loss at Nyquist frequency and a clear eye diagram can be captured at 36 Gb/s.

Continuous‐time linear equalizer with automatic boosting gain adaptation and input offset cancellation

SummaryA continuous‐time linear equalizer (CTLE) for high‐speed serial link is presented whose adaptive boosting gain is obtained with the data and edge values sampled by clock and data recovery circuit. The input offset of the serial link receiver is estimated by the data and edge values as well and cancelled by the CTLE. The adaptation of the CTLE boosting gain is immune to the phase error of the clock and data recovery sampling clock, and the cancellation of the input offset is independent of the boosting gain adaptation. The performance of the proposed adaptive CTLE has been evaluated by applying it to a 5‐Gb/s serial link receiver implemented in a 65‐nm CMOS technology.

A 0.5–16.3 Gbps Multi-Standard Serial Transceiver With 219 mW/Channel in 16-nm FinFET

This paper presents a flexible-reach 0.5–16.3 Gb/s serial transceiver which is integrated into a field-programmable gate array (FPGA) and fabricated in 16-nm FinFET CMOS. The transceiver is fully adaptive to cover the FPGA requirement to support a multitude of combinations of data-rates and standards such as 10 G-KR, PCIe Gen3/4, and SFP+ across a wide range of channel loss profiles. High-performance techniques employed include a fully adaptive continuous-time linear equalizer, automatic gain control, an 11-tap decision feedback equalizer, wideband LC phase-locked loops, and a high-tracking-bandwidth clock and data recovery loop with low latency. Low-power techniques such as half-rate clocking, active inductors and data-rate programmability are employed to meet stringent power budgets at the different rates. At 16.3 Gb/s, the receiver has a jitter tolerance of >0.3UI at 100 MHz. The transceiver achieves a bit error rate < 10e − 15 with up to 28-dB loss at Nyquist. It consumes 219 mW/channel at 16.3 Gb/s. The design has robust performance across process, voltage, and temperature, and the architecture allows for a high degree of tuning to handle different system environments in deployment.

A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method

This brief presents an adaptive continuous-time linear equalizer (CTLE) and one-tap decision feedback equalizer (DFE) using the spectrum balancing (SB) method. The SB method is extended for not only CTLE but also DFE with the aid of gain characteristics of one-tap DFE. Thus, adaptation loops for each equalizer type are merged to a single loop. As a result, the complexity and power consumption of the adaptation circuits are reduced significantly. The test chip consumes 34.2 mW from 1.2 V supply with 65-nm CMOS process.

A 10-Gb/s low-power adaptive continuous-time linear equalizer using asynchronous under-sampling histogram

A 10-Gb/s low-power adaptive continuous-time linear equalizer using asynchronous under-sampling histogram

A 5.4-Gbit/s Adaptive Continuous-Time Linear Equalizer Using Asynchronous Undersampling Histograms

We demonstrate a new type of adaptive continuous-time linear equalizer (CTLE) based on asynchronous undersampling histograms. Our CTLE automatically selects the optimal equalizing filter coefficient among several predetermined values by searching for the coefficient that produces the largest peak value in histograms obtained with asynchronous undersampling. This scheme is simple and robust and does not require clock synchronization for its operation. A prototype chip realized in 0.13-μm CMOS technology successfully achieves equalization for 5.4-Gbit/s 231 - 1 pseudorandom bit sequence data through 40-, 80-, and 120-cm PCB traces and 3-m DisplayPort cable. In addition, we present the results of statistical analysis with which we verify the reliability of our scheme for various sample sizes. The results of this analysis are confirmed with experimental data.