Adaptive Calibration Technique Research Articles

An adaptive calibration technique for thermistor with varying temperature coefficient and reference resistance

Background: A thermistor is a nonlinear sensor requiring a precise calibration technique to achieve accurate temperature measurements. This paper attempts to design a calibration technique employing artificial neural network (ANN) algorithms. The present work fulfills the following objectives: (i) to cover 100% input range in the linearity range measurement; (ii) to make the measurement technique adaptive to variations in reference resistance and thermistor temperature coefficient using a calibration technique. Methods: An ANN-based calibration circuit is cascaded to the data conversion circuit. Optimized ANN is trained with linear data independent of reference resistance and temperature coefficient effects on thermistor output. ANN optimization is performed by comparing various schemes, algorithms, and numbers of hidden layers to achieve a minimum mean square error and a regression close to 1. Results: The proposed technique provides a linear relationship for the system over the entire input range and avoids the requirement of repeated calibrations each time the thermistor is replaced. Practical data are used to validate the proposed measurement technique. Conclusions: The objectives and proposed technique have been demonstrated by results with a root mean square percentage error of 1.8%.

Frequency-Interleaved ADCs With Adaptive Blind Cyclic Calibration

A novel digital adaptive blind calibration technique for frequency-interleaved analog-to-digital converters (FI-ADCs) with arbitrary numbers of channels is proposed. It performs the estimation and correction of multiple inherent circuit deficiencies alternately and recursively in the background, including spectral leakage, harmonic folding, jitter, I/Q mirror and aliasing images, and suffices to deliver projected calibration capabilities with deliberately chosen initial guesses. We are of the opinion that this is the first study to address the joint channel identification and error compensation problem encountered in the FI-ADC design. For the efficient implementation, an analytical time-interleaving-like equivalent model is formulated such that the number of unknown mismatch parameters is significantly reduced, and signals devoted to cyclic estimation are maximally decimated. This derived model not only propounds a better perspective for comprehension and interpretation of the FI system mechanism but also enables sufficient scalability and flexibility of the developed calibration framework. Extensive simulation results further show that this novel architecture achieves a good balance between the computational complexity and convergence, and provides an exceptional and relatively flat effective number of bit (ENOB) performance over a wide bandwidth.

Adaptive analogue calibration technique to compensate electrode motion artefacts in biopotential recording

This study presents an adaptive analogue calibration method to compensate electrode–skin impedance mismatch during biopotential signal (electrocardiogram, electroencephalogram and electromyogram) acquisition with enhanced immunity to electromagnetic interference (EMI). The method continuously measures the variation of the impedance mismatch between the electrode–skin interfaces arising primarily due to motion artefacts, and thereafter compensate for the resulting distortions at the output. The compensation is done with the help a proportional–integral–derivative controller in the feedback loop, together with the acquisition of the biopotential signals. A common mode shunt feedback at the output attenuates the common mode EMI and reduces the common mode deviation. As compared to previously reported techniques, the proposed technique refutes any need for offline manual calibration and shows a significant improvement in EMI attenuation without interrupting the main system's operation. This study explains the proposed technique with the comprising blocks, illustrates the theoretical models and analyses, and evaluates the superior performances of the proposed method by comparing the responses with those obtained from the other EMI-Immune electrode mismatch compensating front-ends existing in the literature.

An Adaptive Colour Calibration for Crowdsourced Images in Heritage Preservation Science

In this paper, an adaptive image calibration technique suitable for cultural heritage surveillance in controlled environments is proposed. Heritage pieces, as objects important to conserve, are prone to degradation and thus in the need of a constant watch in order to assess the moment where maintenance is required, preferably in a non-invasive way. By means of a crowdsourcing approach, we take as surveillance cues the pictures visitors take of the piece under surveillance to avoid the need of a permanent human effort on monitoring. In this paper we propose a novel image calibration approach destined to monitor the state of a cultural heritage piece taking as information cues photographs of different sources. Our technique aims to surpass the colorimetry difference between pictures taken by different cameras, performing an adaptive linear interpolation having a given display with a set of colours as reference values, thus transforming the initial colour space of any picture to a fixed one. This is performed in the RGB domain. Lastly, the pictures are transformed to the CIELAB space to extract the colour coordinates and measure the overall objective quality of the calibration. Acting like this allows the heritage monitoring of its possible degradation along time in an effective way without incurring in expensive resources.

Publisher's Note: "An adaptive calibration technique of timing skew mismatch in time-interleaved analog-to-digital converters" [Rev. Sci. Instrum. 90, 025102 (2019)

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An Adaptive Blind Calibration Technique for Frequency Response Mismatches in M-Channel Time-Interleaved ADCs

This brief proposes a novel adaptive architecture for blind estimation and calibration of the frequency response mismatches in an M-channel time-interleaved analog-to-digital converter (TI-ADC). Based on the basis functions generated from the measured TI-ADC output, the mismatch errors could be reconstructed blindly and subtracted from the TI-ADC output adaptively. The advantage of the proposed technique is that it only needs to know the measured output signal without requiring any additional information and it is applicable to any channel TI-ADCs. Specially, the calibration structure only needs several differentiators with fixed coefficients without requiring a bank of adaptive FIR filters. In addition, the numerical simulations have been presented to demonstrate the effectiveness and superiority of the proposed technique, which shows that the proposed technique can improve the SNR and SFDR by over 25 dB.

An adaptive calibration technique of timing skew mismatch in time-interleaved analog-to-digital converters.

Because of the exponential increase of sampling rate, time-interleaved analog-to-digital converter (TIADC) has a fast growth in the high-speed applications. However, the channel mismatch error is a serious challenge for the performance of TIADC. In this article, we address the timing skew mismatch error and propose a novel adaptive calibration method. The principle and operating process of the calibration algorithm are explained. To validate the proposed technique, we designed a four-channel TIADC-based digital oscilloscope with a sampling rate of 10 GS/s. Based on this instrumentation platform, (i) calibration algorithm was implemented by hardware; and (ii) a test platform consisting of advanced instruments and tools was setup to testify the effect and robustness of proposed algorithm. Moreover, the technical details of instrumentation are described for the first time. The experimental results show that the calibration algorithm significantly suppresses the distortions due to timing skew mismatch error. The TIADC-based instrumentation achieves spurious-free dynamic range of 52.48 dB and effective number of bits of 5.83 bit, respectively. Besides, the complexity of the proposed algorithm is compared and discussed.

An adaptive calibration and beamforming technique for a GEO satellite data relay

SummaryHigh throughput data links from low Earth orbit satellites through a geostationary orbit satellite data relay have been proposed to increase the available contact times to ground stations. Accurate antenna beam pointing and tracking of moving targets are key requirements for the relay satellite. In this work, we propose an adaptive calibration and beamforming methodology on the basis of least mean squares, which is suitable for a geostationary orbit data relay. The target system consists of the combination of a high gain reflector fed by a digitally steerable patch antenna array. The proposed method is first presented by numerical cosimulation of the antenna and the calibration algorithm. The results are then validated in an outdoor experimental setup with all digital signal processing implemented in a field‐programmable gate array. We demonstrate the tracking ability and pointing performance of the digitally enhanced reflector antenna with gain fluctuations smaller than 3 dB over a field of view of at least 2,5°. The demonstrated performance shows that the digitally enhanced reflector antenna is a suitable candidate for long‐distance space communications.

A 0.95-mW 6-b 700-MS/s Single-Channel Loop-Unrolled SAR ADC in 40-nm CMOS

This brief presents a low-power and high-speed single-channel successive approximation register (SAR) analog-to-digital converter (ADC). It uses a loop-unrolled architecture with multiple comparators. Each comparator is used not only to make a comparison but also to store its output and generate an asynchronous clock to trigger the next comparator. The SAR logic is significantly simplified to increase speed and reduce power. The comparator offset and decision time are optimized with a bidirectional single-side switching technique by controlling the input common-mode voltage $V_\mathrm{cm}$ . To remove the nonlinearity due to the comparators' offset mismatch, a simple and effective $V_\mathrm{cm}$ - adaptive offset calibration technique is proposed. The prototype ADC in 40-nm CMOS achieves a 35-dB signal to noise-plus-distortion ratio and a 48-dB spurious-free dynamic range at a 700-MS/s sampling rate. It consumes 0.95 mW, leading to a Walden figure-of-merit (FOM) of 30 fJ/conversion-step and a Schreier FOM of 153.4 dB.

Systematic design and implementation of a high-robust adaptive calibration technique for ETI-induced analog front end circuits in EEG systems

Robustness is a major concern of wearable electroencephalogram (EEG) acquisition systems. It is often closely tied with variations of electrode to tissue interface (ETI), resulting in significant difficulties for following analog front end (AFE) circuitry design and signal processing. To realize a high-robust EEG system and relax the AFE requirements, adaptive ETI characterization and signal calibration techniques are proposed. Instead of monitoring ETI impedance and/or employing an active electrode, this paper demonstrates an attempt to continuously detect dc offset and ac-coupled gain variations of an entire ETI-induced signal acquisition path (ETI-AP). Both additional and multiplicative factors of distorted signals are stabilized by an adaptive coefficient compensation algorithm, which modulates the non-stationary ETI-AP to a constant channel. During EEG measurement, a pseudo-random number sequence generated from a FPGA is driven to body as a test signal to estimate and compensate the ETI-AP characteristic. The proposed techniques were evaluated in lab environments where both spontaneous and evoked EEGs were recorded by using a bipolar montage on a long-haired, healthy adult. Furthermore, foam-covered and pin-based electrodes were placed on the participant's scalp and skin surface in order to establish different ETI conditions. With this proposed technique, the empirical results shown the dynamic variation of non-stationary ETI was continuously characterized; calibrated EEGs achieved higher signal to noise ratio, which demonstrates the validity of the proposed method, as well as its compatibility with diverse sensors and bio-medical acquisition systems.

A Multi-Frequency Multi-Standard Wideband Fractional- PLL With Adaptive Phase-Noise Cancellation for Low-Power Short-Range Standards

This paper presents a wideband fractional- $ { N}$ frequency synthesizer design with a low-effort adaptive calibration technique for $\Sigma \Delta $ quantization noise cancellation. After adopting from the classical single-ended loop filter structure, this least mean square algorithm based calibration technique can precisely and efficiently adjust the noise cancellation digital–analog convertor current with high linearity and immunity. Besides, as long as the desired current is achieved, the calibration circuits are turned off and disconnected to save the power consumption and isolate from the signal paths. With the proposed phase-noise cancellation technique, small area and low power circuit design are achieved, meanwhile the fractional and reference spurs are highly attenuated, allowing the wideband direct frequency/phase modulation with high data rates. With low effort modification, it can be directly implemented as straightforward phase-noise enhancement for any wideband phase-locked loop applications.

A Practically Validated Adaptive Calibration Technique using Optimized Artificial Neural Network for Level Measurement by Capacitance Level Sensor

Design of an adaptive calibration technique using an optimized artificial neural network for liquid-level measurement is discussed in this paper. The objective of the present work is to design and validate an adaptive calibration technique so as (1) to extend the linearity range of measurement to 100% of full-scale input range and (2) to make the measurement technique adaptive of variations in tank diameter, permittivity of liquid, liquid temperature, and to achieve objectives (1) and (2) using an optimized neural network. An optimized artificial neural network is a network having least possible number of hidden layers to achieve minimum mean square error between outputs and targets by comparing various algorithms, schemes, and transfer functions of neuron. The output of capacitance level sensor is capacitance. A data conversion unit is used to convert it to voltage. A suitable optimized artificial neural network is designed and used in place of conventional calibration circuit. The proposed technique is tested with simulated data and validated with practical data. Results show that proposed technique has fulfilled the set objectives.

Support Vector Machine based Adaptive Calibration Technique for Resistance Temperature Detector

Abstract This paper proposes an adaptive calibration technique for temperature measurement using Resistance Temperature Detector (RTD) sensor based on Support Vector Machine (SVM). In practise, RTD has nonlinear response characteristics, and its output varies with variation in RTD. Support vector machine approach is used to design an adaptive calibration technique which (i) produces the output to have a linear mapping relationship to achieve RTD nonlinearity compensation, and (ii) to produce output adaptive to variations in temperature coefficients of RTD and reference resistance. The simulation results show that the proposed technique has fulfilled its set objectives. Since root mean square of percentage error is found to be 0.0015.

A fast AFC technique with self-calibration for fast-locking PLLs

A fast adaptive frequency calibration (AFC) technique with self-calibration for fast-locking phase-locked loops is presented with frequency-selecting switches. The proposed AFC directly calculates the proper switch states of the voltage-controlled oscillator (VCO). It requires only six clock cycles of the reference oscillator regardless of the number of VCO switches to reach the final switch state in the ideal case. The proposed method counts the number of VCO cycles per reference clock period for the minimum VCO frequency (MIN) and the maximum VCO frequency (MAX) during the first four-clock periods. For the following two-clock periods, the proper states of the VCO switches are set to the calculated value from MIN, MAX and the desired division ratio for a target frequency (EST). A frequency synthesiser with the proposed AFC was implemented on a 0.18 µm CMOS process. The AFC time decreased from 40 to 0.4 µs employing the proposed scheme such that the total lock time is 40 µs with the loop bandwidth of 40 kHz.

A wide range sigma—delta fractional-N frequency synthesizer with adaptive frequency calibration

A wide range fractional-N frequency synthesizer in 0.18 μm RF CMOS technology is implemented. A switched-capacitors bank LC-tank VCO and an adaptive frequency calibration technique are used to expand the frequency range. A 16-bit third-order sigma—delta modulator with dither is used to randomize the fractional spur. The active area is 0.6 mm2. The experimental results show the proposed frequency synthesizer consumes 4.3 mA from a single 1.8 V supply voltage except for buffers. The frequency range is 1.44–2.11 GHz and the frequency resolution is less than 0.4 kHz. The phase noise is −94 dBc/Hz @ 100 kHz and −121 dBc/Hz @ 1 MHz at the output of the prescaler with a loop bandwidth of approximately 120 kHz. The performance meets the requirements for the multi-band and multi-mode transceiver applications.

A 3 to 5 GHz low-phase-noise fractional-N frequency synthesizer with adaptive frequency calibration for GSM/PCS/DCS/WCDMA transceivers

A low-phase-noise Σ—Δ fractional-N frequency synthesizer for GSM/PCS/DCS/WCDMA transceivers is presented. The voltage controlled oscillator is designed with a modified digital controlled capacitor array to extend the tuning range and minimize phase noise. A high-resolution adaptive frequency calibration technique is introduced to automatically choose frequency bands and increase phase-noise immunity. A prototype is implemented in 0.13 μm CMOS technology. The experimental results show that the designed 1.2 V wideband frequency synthesizer is locked from 3.05 to 5.17 GHz within 30 μs, which covers all five required frequency bands. The measured in-band phase noise are −89, −95.5 and −101 dBc/Hz for 3.8 GHz, 2 GHz and 948 MHz carriers, respectively, and accordingly the out-of-band phase noise are −121, −123 and −132 dBc/Hz at 1 MHz offset, which meet the phase-noise-mask requirements of the above-mentioned standards.

A Virtual-ADC Digital Background Calibration Technique for Multistage A/D Conversion

A nonlinear adaptive digital calibration technique for multistage analog-to-digital converters (ADCs) is presented. The approach is derived from a replica-path scaling principle inspired by the parallel-ADC equalization architecture. The treatment of residue gain nonlinearities leads to potentially significant power savings for a simple modification of the first ADC stage. The design tradeoffs involved in this technique, particularly a band-limited interpolator employed, are discussed in detail. Computer simulations demonstrate signal-to-noise-plus-distortion-ratio and spurious-free-dynamic-range improvements from 40 to 90 dB and 45 to more than 100 dB, respectively, for a 15-bit pipelined ADC.

Digital Calibration of Nonlinear Memory Errors in Sigma–Delta Modulators

A digital adaptive calibration technique to linearize sigma-delta (ΣΔ) modulators based on an output-referred distortion analysis of discrete-time integrators (DTIs) is presented. A sequential power series (a special form of Volterra series) is found sufficient to model the nonlinear memory errors in a DTI, which entails the application of adaptive polynomial transversal filtering for error correction of the modulator. Error-parameter identification is accomplished by correlating various moments of the digital output with a 1-bit pseudorandom noise, which is injected into the analog input of each DTI of the modulator. Simulations demonstrate the effectiveness of the technique in compensating the signal-dependent errors of first- and second-order ΣΔ modulators.

Adaptive digital calibration techniques for narrow band low-IF receivers with on-chip PLL

Digital calibration and control techniques for narrow band integrated low-IF receivers with on-chip frequency synthesizer are presented. The calibration and control system, which is adopted to ensure an achievable signal-to-noise ratio and bit error rate, consists of a digitally controlled, high resolution dB-linear automatic gain control (AGC), an inphase (I) and quadrature (Q) gain and phase mismatch calibration, and an automatic frequency calibration (AFC) of a wideband voltage-controlled oscillator in a PLL based frequency synthesizer. The calibration system has a low design complexity with little power and small die area. Simulation results show that the calibration system can enlarge the dynamic range to 72 dB and minimize the phase and amplitude imbalance between I and Q to 0.08° and 0.024 dB, respectively, which means the image rejection ratio is better than 60 dB. In addition, the calibration time of the AFC is 1.12 μs only with a reference clock of 100 MHz.

A Wide-Bandwidth 2.4 GHz ISM Band Fractional-$N$ PLL With Adaptive Phase Noise Cancellation

A fast-settling adaptive calibration technique is presented that makes phase noise cancelling DeltaSigma fractional-N PLLs practical for the low reference frequencies commonly used in wireless communication systems. The technique is demonstrated as an enabling component of a 2.4 GHz ISM band CMOS PLL IC with a 730 kHz bandwidth, a 12 MHz reference, and an on-chip loop filter. In addition to the adaptive calibration technique, the IC incorporates a dynamic charge pump biasing technique to reduce power dissipation. The worst-case phase noise of the IC is -101 dBc/Hz and -124 dBc/Hz at 100 kHz and 3 MHz offsets, respectively, and the adaptive phase noise cancellation technique has a worst-case settling time of 35 mus . The IC is implemented in 0.18 CMOS technology. It measures 2.2 x 22 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and its core circuitry consumes 20.9 mA from a 1.8 V supply.