Acyclic Circuits Research Articles

An Equivalent Circuit-Based Approach for Power and Emission Tracing in Power Networks

This article develops an equivalent circuit-based model to perform power and emission tracing in power grids. By relying on the proposed model, a power network can be readily converted into a series of equivalent acyclic circuits so that the contributions of generators to a specific load can be clearly and unequivocally traced from a circuit point of view without making any assumptions on how nodal power inflows contribute to the outflows. The effectiveness of the proposed method is discussed through both power flow and optimal power flow simulations on three case studies, including a simple two-generator network, and the IEEE standard 14-bus and 118-bus systems. Furthermore, the proposed power flow tracing method is used in estimating the electricity-associated emissions from the customer side.

Time-delocalized quantum subsystems and operations: on the existence of processes with indefinite causal structure in quantum mechanics

It has been shown that it is theoretically possible for there to exist higher-order quantum processes in which the operations performed by separate parties cannot be ascribed a definite causal order. Some of these processes are believed to have a physical realization in standard quantum mechanics via coherent control of the times of the operations. A prominent example is the quantum SWITCH, which was recently demonstrated experimentally. However, the interpretation of such experiments as realizations of a process with indefinite causal structure as opposed to some form of simulation of such a process has remained controversial. Where exactly are the local operations of the parties in such an experiment? On what spaces do they act given that their times are indefinite? Can we probe them directly rather than assume what they ought to be based on heuristic considerations? How can we reconcile the claim that these operations really take place, each once as required, with the fact that the structure of the presumed process implies that they cannot be part of any acyclic circuit? Here, I offer a precise answer to these questions: the input and output systems of the operations in such a process are generally nontrivial subsystems of Hilbert spaces that are tensor products of Hilbert spaces associated with systems at different times---a fact that is directly experimentally verifiable. With respect to these time-delocalized subsystems, the structure of the process is one of a circuit with a causal cycle. This provides a rigorous sense in which processes with indefinite causal structure can be said to exist within the known quantum mechanics. I also identify a whole class of isometric processes, of which the quantum SWITCH is a special case, that admit a physical realization on time-delocalized subsystems. These results unveil a novel structure within quantum mechanics, which may have important implications for physics and information processing.

Timing Path-Driven Cycle Cutting for Sequential Controllers

Power and performance optimization of integrated circuits is performed by timing-driven algorithms that operate on directed acyclic graphs. Sequential circuits and circuits with topological feedback contain cycles. Cyclic circuits must be represented as directed acyclic graphs to be optimized and evaluated using static timing analysis. Algorithms in commercial electronic design automation tools generate the required acyclic graphs by cutting cycles without considering timing paths. This work reports on a method for generating directed acyclic circuit graphs that do not cut the specified timing paths. The algorithm is applied to over 125 benchmark designs and asynchronous handshake controllers. The runtime is less than 1 second, even for even the largest published controllers. Circuit timing graphs generated using this method retain the necessary timing paths, which enables circuit validation and optimization employing the commercial tools. Additional benefits show these designs are on an average a third in size, operate 33.3% faster, and consume one-fourth the energy.

Cyclic Boolean circuits

A Boolean circuit is a collection of gates and wires that performs a mapping from Boolean inputs to Boolean outputs. The accepted wisdom is that such circuits must have acyclic (i.e., loop-free or feed-forward) topologies. In fact, the model is often defined this way–as a directed acyclic graph (DAG). And yet simple examples suggest that this is incorrect. We advocate that Boolean circuits should have cyclic topologies (i.e., loops or feedback paths). In other work, we demonstrated the practical implications of this view: digital circuits can be designed with fewer gates if they contain cycles. In this paper, we explore the theoretical underpinnings of the idea. We show that the complexity of implementing Boolean functions can be lower with cyclic topologies than with acyclic topologies. With examples, we show that certain Boolean functions can be implemented by cyclic circuits with as little as one-half the number of gates that are required by equivalent acyclic circuits. We also show a quadratic upper bound: given a cyclic Boolean circuit with m gates, there exists an equivalent acyclic Boolean circuit with m2 gates.

THE ${\mathcal R}$- AND ${\mathcal L}$-ORDERS OF THE THOMPSON–HIGMAN MONOID Mk, 1 AND THEIR COMPLEXITY

We study the monoid generalization Mk, 1 of the Thompson–Higman groups, and we characterize the [Formula: see text]- and the [Formula: see text]-order of Mk, 1. Although Mk, 1 has only one nonzero [Formula: see text]-class and k-1 nonzero [Formula: see text]-classes, the [Formula: see text]- and the [Formula: see text]-order are complicated; in particular, [Formula: see text] is dense (even within an [Formula: see text]-class), and [Formula: see text] is dense (even within an [Formula: see text]-class). We study the computational complexity of the [Formula: see text]- and the [Formula: see text]-order. When inputs are given by words over a finite generating set of Mk, 1, the [Formula: see text]- and the [Formula: see text]-order decision problems are in P. However, over a "circuit-like" generating set the [Formula: see text]-order decision problem of Mk, 1 is [Formula: see text]-complete, whereas the [Formula: see text]-order decision problem is coNP-complete. Similarly, for acyclic circuits the surjectiveness problem is [Formula: see text]-complete, whereas the injectiveness problem is coNP-complete.

Learning Acyclic Probabilistic Circuits Using Test Paths

We define a model of learning probabilistic acyclic circuits using value injection queries, in which fixed values are assigned to an arbitrary subset of the wires and the value on the single output...

Transforming Cyclic Circuits Into Acyclic Equivalents

Designers and high-level synthesis tools can introduce unwanted cycles in digital circuits, and for certain combinational functions, cyclic circuits that are stable and do not hold state are the smallest or most natural representations. Cyclic combinational circuits have well-defined functional behavior yet wreak havoc with most logic synthesis and timing tools, which require combinational logic to be acyclic. As such, some sort of cycle-removal step is necessary to handle these circuits with existing tools. We present a two-stage algorithm for transforming a combinational cyclic circuit into an equivalent acyclic circuit. The first part quickly and exactly characterizes all combinational behavior of a cyclic circuit. It starts by applying input patterns to each input and examining the boundary between gates whose outputs are and are not defined to find additional input patterns that make the circuit behave combinationally. It produces sets of assignments to inputs that together cover all combinational behavior. This can be used to report errors, as an optimization aid, or to restructure the circuit into an acyclic equivalent. The second stage of our algorithm does this restructuring by creating an acyclic circuit fragment from each of these assignments and assembles these fragments into an acyclic circuit that reproduces all the combinational behavior of the original cyclic circuit. Experiments show that our algorithm runs in seconds on real-life cyclic circuits, making it useful in practice.

Learning a circuit by injecting values

We propose a new model for exact learning of acyclic circuits using experiments in which chosen values may be assigned to an arbitrary subset of wires internal to the circuit, but only the value of the circuit's single output wire may be observed. We give polynomial time algorithms to learn (1) arbitrary circuits with logarithmic depth and constant fan-in and (2) Boolean circuits of constant depth and unbounded fan-in over AND, OR, and NOT gates. Thus, both AC0 and NC1 circuits are learnable in polynomial time in this model. Negative results show that some restrictions on depth, fan-in and gate types are necessary: exponentially many experiments are required to learn AND/OR circuits of unbounded depth and fan-in; it is NP-hard to learn AND/OR circuits of unbounded depth and fan-in 2; and it is NP-hard to learn circuits of constant depth and unbounded fan-in over AND, OR, and threshold gates, even when the target circuit is known to contain at most one threshold gate and that threshold gate has threshold 2. We also consider the effect of adding an oracle for behavioral equivalence. In this case there are polynomial-time algorithms to learn arbitrary circuits of constant fan-in and unbounded depth and to learn Boolean circuits with arbitrary fan-in and unbounded depth over AND, OR, and NOT gates. A corollary is that these two classes are PAC-learnable if experiments are available. Finally, we consider an extension of the model called the synchronous model. We show that an even more general class of circuits are learnable in this model. In particular, we are able to learn circuits with cycles.

State minimisation-based loop handling for criticalpath analysis

The authors present a new approach to the critical path analysis of digital circuits with feedback loops. The idea is to first convert a circuit with feedback loops to an equivalent minimum-sized acyclic circuit using a state-minimisation technique of sequential machines and then to perform critical path analysis. The results of experiments illustrate that the proposed method finds critical paths correctly and efficiently in the presence of feedback loops.

The virtual feedback problem in hierarchical representations of combinational circuits

Orders of magnitude of space and time can be saved if hierarchical algorithms are used for automatic synthesis and analysis of regular VLSI circuits. When we tried to apply this technique to compiled simulation of large regular combinational circuits, we observed that hierarchical representations of acyclic circuits often contain cycles. In this paper we study the question of whether this undesired property is necessary or not. We prove, that there are combinational circuits, which have a succinct cyclic hierarchical representation, but where each acyclic hierarchical representation is large. This negative result may be weakened, if we allow the circuits structure to be changed but not its behavior. We also discuss the effect of these observations on hierarchical simulation techniques and the complexity of pragmatic approaches such as the construction of a smallest acyclic refinement of a hierarchical representation.

Planar acyclic computation

This paper considers the following problem: given a specification consisting of a set of variables X , a multiset of functions F on those variables, and a cyclic ordering on X ⌣ F , determine whether or not there exists a planar acyclic circuit which realizes the specification. An algorithm is given which produces such a circuit whenever one exists. In proving that our algorithm meets this requirement we provide some simple mathematical characterizations of those specifications which are realizable.

Hierarchical test generation using precomputed tests for modules

A novel test generation technique for large circuits with high fault coverage requirements is described. The technique is particularly appropriate for circuits designed by silicon compilers. Circuit modules and signals are described at a high descriptive level. Test data for modules are described by predefined stimulus/response packages that are processed symbolically using techniques derived from artificial intelligence. The packages contain sequences of stimulus and response vectors which are propagated as units. Since many test vectors are processed simultaneously, a substantial increase in test generation speed can be achieved. A prototype test generator which uses the technique to generate tests for acyclic circuits has been implemented. Preliminary results from this program suggest that for circuits composed of datapath elements, speed improvements of three orders of magnitude over conventional techniques may be possible. >

Improving the Performance of a Switch-Level Simulator Targeted for a Logic Simulation Machine

This work deals with some performance aspects of the implementation of an algorithm to simulate MOS electronic circuits, modeled at the transistor level. The target architecture is a special purpose logic simulation machine, the Yorktown Simulation Engine (YSE), which has no direct support for loop mechanisms or conditional flow control. Since the simulation algorithm requires such mechanisms to determine whether and when a circuit reaches a steady state, we must calculate prior to simulation time, the number of iterations required for the algorithm to converge. We show how to arrange the order in which transistors are processed, aiming at a reduced number of such iterations, and therefore, an improved simulation performance. The results presented here show the optimal way to deal with acyclic circuits and some heuristic criteria to handle cyclic circuits. Also, we show a method to calculate the number of iterations required for the convergence of the simulation algorithm. These methods, originally developed for the YSE, have been also incorporated in a switch level simulator running on an IBM/370 architecture.