Actual Computer System Research Articles

A Scheme for Evaluating XML Engine on RDBMS

There are an increasing number of DBMS vendors thinking of integrating XML data management into traditional relational database, with wider use of XML. In this case, a comprehensive evaluation methodology is needed to evaluate the XML engine in RDBMS correctly. In this paper, we analyze the characteristics of XML engine and propose an evaluation strategy of XML engine in a RDBMS. We believe that the evaluation should include functional evaluation and performance evaluation, and cover several major aspects of DB such as storage, query and update. Then we designed an evaluation scheme for the XML engine in RDBMS according the strategy. The scheme describes an evaluation scene and contains a data set, workload and index set. The data set reflects the characteristics of both data-centric and document-centric XML data. The workload covers all of the requirements of XQuery in W3C. The index set covers the aspects of storage, indexing, query and update. In the end, we complete an experiment to test an actual computer system using the proposal. The result shows that the proposal is proper. Index Terms—DBMS; XML; W3C; XQuery; Evaluation

Predicting the intrusion intentions by observing system call sequences

Identifying the intentions or attempts of the monitored agents through observations is very vital in computer network security. In this paper, a plan recognition method for predicting the anomaly events and the intentions of possible intruders to a computer system is developed based on the observation of system call sequences. The probability of the goal state for a system call sequence is defined as the prediction index to determine if the intention is normal. An efficient algorithm based on the dynamic Bayesian network theory with parameter compensation is derived and then applied to update the index recursively. Extensive empirical testing is performed on the data sets published in the literature and those collected in an actual computer system at our lab. The testing results showed that this method can identify the intrusion behaviors from the observed system call sequences with good accuracy.

Solder joint reliability of high I/O ceramic-ball-grid arrays and ceramic quad-flat-packs in computer environments: the PowerPC 603/sup TM/ and PowerPC 604/sup TM/ microprocessors

Recent trends in wafer fabrication techniques have produced devices with smaller feature dimensions, increasing gate count and chip inputs/outputs (I/Os). This trend has placed increased emphasis on microelectronics packaging. Surface-mountable packages such as the ceramic quad-flat-pack (CQFP) have provided solutions for many high I/O package issues. As the I/O count gets higher, the pitch has been driven smaller to the point where other solutions also become attractive. Surface-mountable ceramic-ball-grid array (CBGA) packages have proven to be good solutions in a variety of applications as designers seek to maximize electrical performance, reduce printed-circuit board real estate, and improve manufacturing process yields. In support of the PowerPC 603 and PowerPC 604 microprocessors, 21 mm CBGA (255 I/Os) and 32 mm (240 I/Os) and 40 mm (304 I/Os) CQFPs are being utilized. Both package types successfully meet computer environment applications. This paper describes test board assembly processes, accelerated thermal stress test setup, and solder joint failure criteria. Failure mechanisms for both packaging technologies will also be presented. The packages discussed in this paper were subjected to two accelerated thermal cycling conditions: 0 to 100/spl deg/C and -40 to 125/spl deg/C. The failure data are plotted using Weibull distributions. The accelerated failure distributions were used to predict failure distributions in application space for typical PowerPC 603 and PowerPC 604 microprocessors computer environments. To predict solder joint reliability of surface-mount technology, a key parameter is: the temperature rise above ambient at the solder joint, /spl Delta/T. In-situ field temperature measurements were taken for a range of computer platforms in an office environment, at the central-processing units. Printed-circuit boards (PCB) were not uniform, therefore only maximum temperature regions of the board were measured. These maximum temperatures revealed the mean to be less than 20/spl deg/C above ambient (i.e., /spl Delta/T<20/spl deg/C) regardless of the power of the device. The largest /spl Delta/T measured in any system was less than 30/spl deg/C above ambient. These temperature measurements of actual computer systems are in close agreement with IPC-SM-785. By utilizing the measured PCB temperature rise, solder joint fatigue life was calculated for the 21 mm ceramic ball-aid-array (CBGA), the package for the PowerPC 603/sup TM/ and PowerPC 604/sup TM/ RISC microprocessors. The average on-off /spl Delta/T for most computer applications is approximately 20/spl deg/C. For an average on-off /spl Delta/T of 30/spl deg/C, the 21 mm CBGA has an estimated fatigue life of over 25 years while the 32 mm and 40 mm CQFP's have an estimated fatigue life of over 50 years.

Seismic Evaluation Method of a Process Computer System for Nuclear Power Plants.

In order to maintain the functional capability of a process computer system used in nuclear power plant, it is necessary to keep both structural integrity and information processing function during design earthquake.Based on failure mode analysis of the process computer system against the earthquake, a method of evaluating functional capability of process computer system is proposed. In this method, the acceleration responses of computer equipment are calculated by FEM and compared with the allowable accelerations obtained by the seismic proving test. The proposed method is examined its usefulness in evaluating the functional capability of an actual process computer system in a nuclear power plant and its validity is verified.

State transition analysis: a rule-based intrusion detection approach

The paper presents a new approach to representing and detecting computer penetrations in real time. The approach, called state transition analysis, models penetrations as a series of state changes that lead from an initial secure state to a target compromised state. State transition diagrams, the graphical representation of penetrations, identify precisely the requirements for and the compromise of a penetration and present only the critical events that must occur for the successful completion of the penetration. State transition diagrams are written to correspond to the states of an actual computer system, and these diagrams form the basis of a rule based expert system for detecting penetrations, called the state transition analysis tool (STAT). The design and implementation of a Unix specific prototype of this expert system, called USTAT, is also presented. This prototype provides a further illustration of the overall design and functionality of this intrusion detection approach. Lastly, STAT is compared to the functionality of comparable intrusion detection tools. >

Development of a 3-Dimensional Seismic Isolation Floor for Computer Systems.

This paper presents a 3-dimensional seismic isolation floor developed to protect computer systems in nuclear power plants from strong earthquakes. The 3-dimensional seismic isolation floor consists of floor panels, a floor frame, horizontal coil springs, isolation-supporting devices and devices for controlling rocking motion. In order to examine the performance of the 3-dimensional isolation floor, vibration tests of an isolation floor model, on which an actual computer system was set up, were carried out using a 3-dimensional shaking table. Test results confirmed that the actual computer system was effectively isolated by the 3-dimensional seismic isolation floor.Moreover, an analytical model was validated against these test results. For the analytical simulation the floor frame was representdd by five lumped masses and the isolation device was modeled as 2-dimensional springs and dampers. Both the calculated acceleration time history and floor response spectrum agree well with test results.

The architecture and operational characteristics of the VMX host machine

The VMX host machine is a hardware-firmware environment for implementation of actual computer systems with a favorable price performance ratio. The article presents the host framework architecture, together with all units which are used to build actual systems. The advantages and future potential of the architecture is briefly discussed. The notion of memory directives within the frame-work of an active (or “intelligent”) memory unit is introduced. This notion serves as one example of the possibilities that are built into the architecture of the VMX host.

Use of data abstraction in process specification

Processes in computer systems are often intimately involved with various data abstractions that occur in the systems. The specification of such processes should state the nature of this involvement. This note focuses on a special kind of process, called a realization process, and its specification because it appears to capture the interplay between concurrency and abstraction in a natural way. A realization process has two important properties: it is &lt;u&gt;transparent&lt;/u&gt; to the abstract space and it is &lt;u&gt;serializable&lt;/u&gt; with processes at the abstract level. Transparency and serializability are the main specifications of realization processes. These concepts are illustrated by an example of the kind of realization processes found in actual computer systems which serves to motivate the discussion.

BASICl—a simple computer to introduce computer organization and assembler language programming

BASICl is a simple interactive assembler-loader/interpreter which has been used as an instructional tool for the introductory course in computer organization and assembler language programming offered by the Computer Science Department at Washington State University. Both “hardware” and software are organized so as to emphasize basic concepts and to eliminate the confusion which occurs when these concepts are first introduced surrounded by the myriad of machine and assembler language-dependent details of an actual computer system. BASIC1 a decimal machine, has a small single address instruction repertoire with a trace, dump, reasonable diagnostics and run time interactive debugging capability. An associated simulator, called TESTER serves to evaluate whether and how well the students' programs have worked.

Survey of analytic queueing network models of computer systems

A number of case studies involving the use of queueing network models to investigate actual computer systems are surveyed. After suggesting a framework by which case studies can be classified, we contrast various parameter estimation methods for specifying model parameters based on measurement data. A tabular summary indicates the relationships among nineteen case studies.

Survey of analytic queueing network models of computer systems

A number of case studies involving the use of queueing network models to investigate actual computer systems are surveyed. After suggesting a framework by which case studies can be classified, we contrast various parameter estimation methods for specifying model parameters based on measurement data. A tabular summary indicates the relationships among nineteen case studies.

Probabilistic models of computer deadlock

As the number of processes and resources increases within a computer system, does the probability of that system's encountering deadlock increase or decrease? The problem of deadlock in computer systems and a model applicable to the investigation of this problem are presented. The model treats sequences of resource activity as potential members of the set of strings accepted by a probabilistic automaton. This paper, after explaining the model and its application, describes a transformation on the automaton which makes it amenable to calculations of the probability of deadlock. These calculations consist of: 1. 1. Derivation of necessary and sufficient conditions for an automaton to be well-behaved —formally described as accepting a normalized language; 2. 2. Usage of these conditions to yield closed-form equations of deadlock probability under several definitions thereof. Although the automaton model used in these calculations is a probabilistic pushdown automaton, it is indicated that the procedures described can also be applied to other types of probabilistic automata modeling other deadlock situations. Results of calculations on actual computer system models are also described, indicating that within the types of systems considered, the probability of deadlock increases.

An Experimental Study and Optimization of Operating Systems

This paper is devoted to experimental study of operating systems through. software measurements. The basic stages of experimental studies are considered. Software monitor ATOM which is flexible measurement tool to obtain detailed data on the actual computer system performance is described. The ATOM is used to study an ICL System 4-70 J-level disk operating system with the use of programs activity trace and input/output trace. The bottlenecks of the system and various ways of tuning and optimization are studied.