Active Neutral Point Clamped Topology Research Articles

EFFECT OF VOLTAGE STRESS ON RELIABILITY OF THE 3-LEVEL ANPC MULTILEVEL INVERTER FOR WIND TURBINES

Wind power with low or no greenhouse gas emissions has been highly prevalent over the last decade. Modern renewable energy systems rely heavily on power electronic devices such as multilevel converters (MLC) to integrate renewables into the grid or provide electricity to islanding loads. These converters’ power electronic switches have a high failure rate (approximately 34 percent). As a result, the reliability evaluation of these converters is vital. Most research has focused on developing a fault-tolerant, efficient and cost-effective topology that reduces components. Still, the reliability of these topologies has received relatively little attention. This paper studies the effect of voltage stress on three-level Active Neutral Point Clamped (ANPC) multilevel inverter reliability. The series redundancy is introduced in ANPC using redundant outer switches, making ANPC a fault-tolerant topology. The reliability of this fault-tolerant topology is compared with the fault-intolerant ANPC. The voltage stress factor is calculated for fault intolerant and proposed fault-tolerant ANPC topologies. Because of the reduced stress on the switches and redundant configuration of the outer switches, the proposed fault-tolerant ANPC is more reliable. The fault-tolerant topology proposed in this paper has the lowest voltage stress factor, resulting in better reliability.

State-of-the-Art 800 V Electric Drive Systems: Inverter–Machine Codesign for Energy Efficiency Optimization

This paper introduces a state-of-the-art inverter–machine codesign methodology for achieving an energy-efficient electric drive system. The methodology is applied in an optimal design case study with the context of the latest trend in the 800 V system. To reduce the voltage rating, a three-level active neutral point clamped topology is utilized in the inverter design, incorporating silicon carbide technology for high-speed operation. This combination allows for efficient power conversion with reduced losses. In the machine design, the increased number of poles that can be achieved in the design phase, along with the utilization of high-speed switching frequencies, enables the development of more efficient machines. Based on the design of the experiment method, by optimizing the parameters of both the inverter and machine simultaneously, using a cosimulation model, the 7.7% of total energy loss during drive cycle operation can be improved.

Single-Phase 5-Level Split-Midpoint Cross-Clamped (5L-SMCC) Inverter: An Alternative to the Two-Stage ANPC Topology

The conventional active neutral-point-clamped (ANPC) multilevel inverters are popular for single-phase applications owing to their advantage of mitigating high-frequency common-mode voltage (CMV). With the ac neutral connected to the midpoint of dc link, their voltage gain is restricted to only half. For boosting output voltage, a two-stage structure by adding a frontend dc–dc boost converter is commonly used. This article investigates the performance of the conventional two-stage 5-level ANPC inverter and proposes an improved topology by splitting the dc-link midpoint and cross clamping them to the dc-link capacitors. While using the same number of power devices and retaining the advantages of the conventional two-stage 5-level ANPC topology, such as high-frequency CMV mitigation and continuous dc source current, the proposed 5-level split-midpoint cross-clamped (5L-SMCC) inverter achieves several advantages, such as higher voltage gain, lower voltage across dc-link capacitors, lower inverter voltage stress, and natural voltage balancing for all capacitors without requiring any balancing controller or sensor. In addition, it saves one capacitor by eliminating the flying capacitor of the conventional 5-level ANPC inverter. The operation of the proposed 5L-SMCC inverter is thoroughly analyzed. For validation, simulation and experimental results are presented.

A Hybrid Active Neutral Point Clamped Inverter Utilizing Si and Ga2O3 Semiconductors: Modelling and Performance Analysis.

In this paper, the performance of an active neutral point clamped (ANPC) inverter is evaluated, which is developed utilizing both silicon (Si) and gallium trioxide (Ga2O3) devices. The hybridization of semiconductor devices is performed since the production volume and fabrication of ultra-wide bandgap (UWBG) semiconductors are still in the early-stage, and they are highly expensive. In the proposed ANPC topology, the Si devices are operated at a low switching frequency, while the Ga2O3 switches are operated at a higher switching frequency. The proposed ANPC mitigates the fault current in the switching devices which are prevalent in conventional ANPCs. The proposed ANPC is developed by applying a specified modulation technique and an intelligent switching arrangement, which has further improved its performance by optimizing the loss distribution among the Si/Ga2O3 devices and thus effectively increases the overall efficiency of the inverter. It profoundly reduces the common mode current stress on the switches and thus generates a lower common-mode voltage on the output. It can also operate at a broad range of power factors. The paper extensively analyzed the switching performance of UWBG semiconductor (Ga2O3) devices using double pulse testing (DPT) and proper simulation results. The proposed inverter reduced the fault current to 52 A and achieved a maximum efficiency of 99.1%.

Novel Five-Level ANPC Bidirectional Converter for Power Quality Enhancement during G2V/V2G Operation of Cascaded EV Charger

This paper presents a novel single-phase (SP) active-neutral point clamped (ANPC) five-level bidirectional converter (FLBC) for enhancing the power quality (PQ) during the grid-to-vehicle (G2V) and vehicle-to-grid (V2G) operation of an electric vehicle (EV) charger connected in series. This EV charger is based on a dual-active half-bridge DC-DC converter (DAHBC) with a high frequency isolation transformer. Unlike the comparable ANPC topologies found in literature, the proposed one has two more switches, i.e., ten instead of eight. However, with the addition of these components, the proposed multilevel converter not only becomes capable of properly balancing the voltage of the DC-link split capacitors under various step-changing conditions but it achieves a better efficiency, a lower stress of the switching devices and a more even distribution of the power losses. The resulting grid-tied ANPC-SPFLBC and DAHBC are accurately controlled with a cascaded control strategy and a single-phase shift (SPS) control technique, respectively. The simulation results obtained with MATLAB-SimPowerSystems as well as the experimental results obtained in laboratory validate the proposed ANPC-SPFLBC for a set of exhaustive tests in both V2G and G2V modes. A detailed power quality analysis carried out with a Fluke 43B alike demonstrates the good performance of the proposed topology.

Topology, Modeling and Control Scheme for a new Seven-Level Inverter With Reduced DC-Link Voltage

This paper presents a novel single-source three-phase multilevel converter with voltage boosting capability for medium-voltage photovoltaic applications. This converter consists of different switched-capacitor networks, formed by 1 capacitor and 3 active switches, as a basic switching cell to generate variable dc-link voltage that boosts the input dc-source voltage, producing 2n+1 (n2) voltage levels at the output. It can reduce the dc-link voltage requirements by 50% in comparison to the traditional neutral point clamped (NPC), flying capacitors, active NPC (ANPC), hybrid and hybrid clamped ANPC and cascaded H-bridge topologies, and 75% to advanced ANPC topologies. It can also reduce the number of required switches and capacitors as well as their voltage stresses compared to these state-of-the-art topologies reported in the literature so far. A finite control set model predictive control algorithm is derived to control the converter, which has the capability to control the active and reactive power without distorting the generated grid current quality. The capacitor voltage balancing is inherent in the proposed topology, and thus, there is no need for any additional voltage balancing circuit, which reduces the control complexity. As an example, a 7-level version of the proposed topology is compared to other existing 7-level inverter topologies.

A new family of boost active neutral point clamped inverter topology with reduced switch count

A new family of inverter topology for active neutral point clamped (ANPC) is proposed. The traditional ANPC gives the output voltage of half the input voltage which necessitates the use of higher input dc-link voltage. To fix this problem, a floating capacitor is used to increase the voltage of the output, which decreases the dc-link requirement. Moreover, no sensors are needed to stabilize the floating condenser for the proposed topology, which minimizes inverter complexities. The neutral point is connected directly to the load terminals, which decreases the leakage current and makes it suitable for solar PV integration. Two modes of operation of the proposed topology have been discussed while considering the voltage of the floating capacitor used in the topology. Furthermore, two extensions of the proposed topology with generalized structure have also been provided in the paper. A detailed comparison with similar topologies has been provided. The level-shifted pulse width modulation technique has been used for the control of the proposed active neutral point clamped topology. In order to illustrate the idea of the proposed active neutral point clamped inverter, the theory of operation and analysis is accompanied by simulation, and experimental waveforms obtained from a laboratory prototype are provided.

Elimination of Abnormal Output Voltage in a Hybrid Active NPC Inverter

This article proposes a method to eliminate abnormal output voltages generated in three-level hybrid active neutral-point clamped (ANPC) inverters. The hybrid ANPC inverter is a topology in which silicon (Si) devices are replaced with silicon-carbide (SiC) devices in part from the conventional ANPC topology. The hybrid ANPC inverters have the advantages of high switching frequency and low power switching loss due to the SiC devices. In this hybrid ANPC inverter, abnormal output voltages occur when the polarity of the output pole voltage is changed from positive to negative. The cause of the abnormal voltages is the switching time difference between the Si and SiC devices, and it is various from a few nanoseconds to a few microseconds. These abnormal output voltages need to be eliminated as it leads to degraded output power quality in the hybrid ANPC inverters. The proposed switching method effectively eliminates the abnormal output voltages and reduces output current distortion. The performance of the proposed method is verified using a prototype of the new three-level hybrid ANPC inverter type through both simulations and experiments.

Active Voltage Balancing and Thermal Performance Analysis of Dual Flying-Capacitor Active Neutral-Point-Clamped (DFC-ANPC) Inverters

Multilevel inverters provide appealing advantages such as improved efficiency, superior thermal performance, better distribution of the switching and conduction power losses, smaller size of passive components including output ac filters and EMI filters, as compared to their two-level counterparts. The flying-capacitor (FC)-based topologies are attaining more attentions, and are finding lots of medium-voltage and low-voltage industrial and residential applications. The FC-based active neutral-point-clamped (ANPC) inverter, as a hybrid topology based on the three-level ANPC and the FC-based configurations, offers outstanding advantages including the reduced number of FCs as well as switching power cells, improved efficiency, and enhanced power quality. However, the utilization of high-voltage line-frequency switches, as a major drawback, hinders the ANPC converter from expansion and penetration into the high-voltage ranges. The dual flying-capacitor (DFC)-ANPC topology resolves this issue through introducing the zero-voltage-switching (ZVS) feature into the line-frequency devices. This soft-switching makes it possible to use the series connection of several low-voltage devices for the realization of the high-voltage switches without having the transient voltage imbalance issues. This article studies the thermal benefits that are achieved in the DFC-ANPC topology alongside the ZVS operation of its line-frequency high-voltage switches. Furthermore, an active voltage balancing technique, based on logic-equations, is proposed in this article for control of the FCs' voltages. The experimental results are provided to validate the improved thermal performance of the DFC-ANPC topology as well as the active balancing technique for the regulation of the FC voltages.

Analysis and Design of a Novel Six-Switch Five-Level Active Boost Neutral Point Clamped Inverter

This article presents an analysis and design of a new boost type six-switch five-level (5L) active neutral point clamped (ANPC) inverter based on switched/flying capacitor technique with self-voltage balancing. Compared to major conventional 5L inverter topologies, such as neutral point clamped, flying capacitor, cascaded H-bridge, and ANPC topologies, the new topology reduces the dc-link voltage requirement by 50%. Whilst reducing the dc-link voltage requirement, the number and the size of the active and passive components are also reduced without compromising the reactive power capability. The analysis shows that the proposed topology is suitable for wide range of power conversion applications (for example, rolling mills, fans, pumps, marine appliances, mining, tractions, and most prominently grid-connected renewable energy systems). Experimental results from a 1.2 kVA prototype justifies the concept of the proposed inverter with a conversion efficiency of around 97.5% ± 1% for a wide load range.

Generalized Phase-Shift PWM for Active-Neutral-Point-Clamped Multilevel Converter

The multilevel active-neutral-point-clamped (ANPC) converters have more control freedoms compared to the conventional neutral-point-clamped topology due to increased switching redundancies. However, the device utilization of level-shift pulsewidth modulation (PWM) is inherently low, and the scalability of space-vector-based PWM is challenging to realize for high-level (e.g., four-level or five-level) topologies. In this article, a novel phase-shift PWM and the design approach for ANPC converter are proposed to handle these two problems simultaneously. The proposed idea enables the modular phase-shift PWM design based on the switch group concept. In such a way, the complexity in the PWM design process can be significantly reduced with enhanced scalability for both the general and simplified ANPC topologies. Moreover, compared with conventional level-shift PWM, the proposed PWM schemes can fully utilize the devices for better loss distribution and higher equivalent switching frequency. Study cases have been done regarding output features, device utilizations, loss distributions, etc., through experimental verification and thorough discussions.

Hybrid 7-Level Boost Active-Neutral-Point- Clamped (H-7L-BANPC) Inverter

The emerging active-neutral-point-clamped (ANPC) inverters with voltage-boosting capability are attractive for their low dc-link voltage requirement. These low voltage requirements enable a single-stage dc-ac power conversion, which improves the overall efficiency, reliability, and power density of the system. A high voltage gain of 1.5 was demonstrated in recent boost type ANPC topology; however, it was achieved at the expense of high voltage stress on some of its switching devices. This brief proposes an improved topology with reduced voltage stress and a lower number of components while retaining the merits of high voltage gain. The proposed topology is a hybrid of a T-type inverter and an H-bridge, which require only one floating capacitor and one less power switch than the aforementioned topology. One floating capacitor with self-voltage balancing capability is integrated to generate 7 output voltage levels. The proposed topology is analyzed and compared with recent boost ANPC topologies. Experimental results are presented for validation.

A Novel Seven-Level Active Neutral-Point-Clamped Converter With Reduced Active Switching Devices and DC-Link Voltage

This paper presents a novel seven-level inverter topology for medium-voltage high-power applications. It consists of eight active switches and two inner flying capacitor (FC) units forming a similar structure as in a conventional active neutral-point-clamped (ANPC) inverter. This unique arrangement reduces the number of active and passive components. A simple modulation technique reduces cost and complexity in the control system design without compromising reactive power capability. In addition, compared to major conventional seven-level inverter topologies, such as the neutral point clamped, FC, cascaded H-bridge, and ANPC topologies, the new topology reduces the dc-link voltage requirement by 50%. This recued dc-link voltage makes the new topology appealing for various industrial applications. Experimental results from a 2.2-kVA prototype are presented to support the theoretical analysis presented in this paper. The prototype demonstrates a conversion efficiency of around 97.2% ± 1% for a wide load range.

Dual-T-Type Seven-Level Boost Active-Neutral-Point-Clamped Inverter

The conventional three-level active-neutral-point-clamped (ANPC) inverter requires high dc-link voltage at least twice the peak of ac output. To reduce the dc-link voltage, a recent topology that enhanced the voltage gain from half to unity has been presented. In this letter, an alternative ANPC topology is established by using two T-type inverters. Two floating capacitors with self-voltage balancing capability are integrated to achieve a voltage-boosting gain of 1.5. In addition, the proposed topology is capable of generating seven voltage levels. Its operation is validated through circuit analysis followed by experimental results of a prototype.

An Optimized Temperature Sensor Calorimetric Power Device Loss Measurement Method

In the optimized design of power converters, loss analysis of power devices is important. Compared with estimation methods, measuring the power device loss directly in the circuit under test is more accurate. The loss measurement method can be divided into two categories: electrical measurement and calorimetric measurement. The accuracy of the electrical measurement result is restricted to the accuracy of the measurement equipment and parasitic parameters, especially for fast switching devices like SiC devices. The results obtained from calorimetric measurement are more convincing. Based on the measurement principle, calorimetric measurement can be divided into four categories: flow density measurement, temperature equivalent measurement, double jacket measurement, and temperature sensor measurement. This paper proposes an optimized temperature sensor measurement method, which has shorter time consumption, a simpler setup, and lower cost. The principles of the optimized method are described and compared with the traditional ways in detail to show its advantages. The loss measurement and error analysis are carried out in a three-level ANPC (active neutral-point-clamped) topology experiment platform based on the SiC&Si hybrid module to prove the accuracy and practicability of this method.

Design and Comparison of Cascaded H-Bridge, Modular Multilevel Converter, and 5-L Active Neutral Point Clamped Topologies for Motor Drive Applications

This paper presents the design procedure and comparison of converters currently used in medium-voltage high-power motor drive applications. For this purpose, the cascaded H-bridge (CHB), modular multilevel converter (MMC), and five-level active neutral point clamped (5-L ANPC) topologies are targeted. The design is performed using 1.7-kV insulated gate bipolar transistors (IGBTs) for CHB and MMC converters, and utilizing 3.3- and 4.5-kV IGBTs for 5-L ANPC topology as normally done in industry. The comparison is done between the designed converter topologies at three different voltage levels (4.16, 6.9, and 13.8 kV, with only the first two voltage levels in case of the 5-L ANPC) and two different power levels (3 and 5 MVA), in order to elucidate the dependence of different parameters on voltage and power rating. The comparison is done from several points of view such as efficiency, capacitive energy storage, semiconductor utilization, parts count (for measure of reliability), and power density.

A New PWM Strategy for Grid-Connected Half-Bridge Active NPC Converters With Losses Distribution Balancing Mechanism

Photovoltaic systems technological development is driven by the request for higher efficiency and safety. These concerns influence also the choice of the power converter stage. Several topologies have been proposed and many of them are available commercially. Among them, the neutral point clamped (NPC) and derived topologies offers high efficiency, low leakage current, and low EMI. However, one main disadvantage of the NPC inverter is given by an unequal distribution of the losses in the semiconductor devices, which leads to an unequal distribution of temperature that can affect lifetime. By using the active NPC (ANPC) topology, where the clamping diodes are replaced by bidirectional switches, the power losses distribution problem is alleviated. The modulation strategy is a key issue for losses distribution in this topology. In this paper, two known strategies are discussed and a new PWM strategy, namely the adjustable losses distribution is proposed for better losses distribution in the ANPC topology. Simulations and experimental results help in evaluating the modulation strategies.

The Common Cross-Connected Stage for the 5L ANPC Medium Voltage Multilevel Inverter

Rising interest in multilevel applications has triggered new research activities. This paper proposes a novel multilevel power electronics building block (PEBB) for the five-level active neutral point clamped (ANPC) multilevel voltage source inverter. The PEBB is composed of six switches in a crossed configuration and one capacitor. It is common to the three phases of a five-level ANPC topology, enabling a large number of levels to be generated. This PEBB is meant to be a reliable upgrade to the 5L topology, increasing output signal quality and reducing the size of the output filter in medium voltage applications. The number of levels generated by the common cross-connected stage (C <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> S) PEBB and the ANPC depends on the voltage ratios chosen between the phase capacitors of the ANPC and the PEBB capacitor(s). The tradeoff stands between the ability to balance the capacitors, the rated blocking voltage of the devices, and the number of levels produced. Under a given configuration, nine levels can be produced, with the possibility to balance the capacitors up to modulation indexes in the region of <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</i> = 0.92. The analysis of the general topology, the description of the nine-level case, and simulation results are first presented. Prototyping results are then shown, and they validate the introduced concept and topology.