Active Memory Systems Research Articles

From jamais to déjà vu: The respective roles of semantic and episodic memory in novelty monitoring and involuntary memory retrieval.

Barzykowski and Moulin's model proposes that déjà vu and involuntary autobiographical memories are the result of a continuously active memory system that tracks the novelty of situations. Déjà vu would only have episodic content and concern interpretation of prior experiences. We argue that these aspects of the model would gain to be clarified and explored further and we suggest possible directions.

Working Memory, Process ing Speed and General Intelligence: Possible Models of Relations with Visuospatial Working Memory Using the Visuospatial Computerized Working Memory Battery (BIMeT-VE)

Abstract Working memory is an active memory system serving the realization of complex cognitive tasks. Over the last decades' research has centered on studying the relationship of this memory system or any of its components with different cognitive functions, such as intelligence. The aim of this study is to analyze the relation between visuospatial working memory, processing speed and general intelligence, and the possible mediation role of some of these variables. To carry out this work, two studies were conducted. On Study 1 participated212 Spanish speaking college students, and a Spanish visuospatial working memory battery was designed and validated -the visuospatial Computerized Working Memory Battery (Bateria Informatizada de Memoria de Trabajo Viso-Espacial; BIMeT-VE)-. On Study 2 participated 114 Spanish speaking college students, and the relationship among visuospatial working memory, processing speed and general intelligence was analyzed. The results showed that general intelligence is directly supported by the processing speed and to maintain visuospatial information for short periods of time, and indirectly by the ability to concurrently process visuospatial information.

Working Memory Structure in Children: Comparing Different Models During Childhood

Working Memory (WM) is an active memory system responsible for the temporary storage and concurrent processing of information. Different authors have considered WM as a complex but unitary system, whereas others have suggested that the system is multidimensional. In this line, the model developed by Baddeley and Hitch (1974) is one of the most well known; it proposes two modality-specific components - the phonological loop and the visuo-spatial sketchpad - and a supervisory executive system - the central executive. This paper contributes to the debate on WM structure by investigating three groups of children of different ages and assessing different models using confirmatory factor analysis. The Working Memory Assessment Battery Test (Alloway, 2007; Injoque-Ricle, Calero, Alloway & Burin, 2011) was administered to 180 monolingual Spanish-speaking children. The three age groups consisted of 6-, 8-, and 11-year-old children (n = 60 participants per group). The results suggest that the WM structure is not uniform across the different age groups tested, showing progressive differentiation and specialization during childhood. This structure would appear to form between the ages of 6 and 8 years and become more complex as adolescence is approached.

Estructura de la memoria operativa: comparando diferentes modelos en la infancia

Working Memory (WM) is an active memory system responsible for the temporary storage and concurrent processing of information. Different authors have considered WM as a complex but unitary system, whereas others have suggested that the system is multidimensional. In this line, the model developed by Baddeley and Hitch (1974) is one of the most well known; it proposes two modality-specific components - the phonological loop and the visuo-spatial sketch pad - and a supervisory executive system - the central executive. This paper contributes to the debate on WM structure by investigating three groups of children of different ages and assessing different models using confirmatory factor analysis. The Working Memory Assessment Battery Test (Alloway, 2007; Injoque-Ricle, Calero, Alloway & Burin, 2011) was administered to 180 monolingual Spanish-speaking children. The three age groups consisted of 6-, 8-, and 11-year-old children (n = 60 participants per group). The results suggest that the WM structure is not uniform across the different age groups tested, showing progressive differentiation and specialization during childhood. This structure would appear to form between the ages of 6 and 8 years and become more complex as adolescence is approached.

Architectural support for uniprocessor and multiprocessor active memory systems

We introduce an architectural approach to improve memory system performance in both uniprocessor and multiprocessor systems. The architectural innovation is a flexible active memory controller backed by specialized cache coherence protocols that permit the transparent use of address remapping techniques. The resulting system shows significant performance improvement across a spectrum of machine configurations, from uniprocessors through single-node multiprocessors (SMPs) to distributed shared memory clusters (DSMs). Address remapping techniques exploit the data access patterns of applications to enhance their cache performance. However, they create coherence problems since the processor is allowed to refer to the same data via more than one address. While most active memory implementations require cache flushes, we present a new approach to solve the coherence problem. We leverage and extend the cache coherence protocol so that our techniques work transparently to efficiently support uniprocessor, SMP and DSM active memory systems. We detail the coherence protocol extensions to support our active memory techniques and present simulation results that show uniprocessor speedup from 1.3 to 7.6 on a range of applications and microbenchmarks. We also show remarkable performance improvement on small to medium-scale SMP and DSM multiprocessors, allowing some parallel applications to continue to scale long after their performance levels off on normal systems.

A performance perspective on the Active Memory System

One major problem of using Java in real-time and embedded devices is the non-deterministic turnaround time of dynamic memory management systems (memory allocation and garbage collection). For the allocation, the non-determinism is often contributed by the time to perform searching, splitting, and coalescing. For the garbage collection, the turnaround time is usually determined by the size of the heap, the number of live objects, the number of object collected, and the amount of garbage collected. Even with the current state-of-the-art garbage collectors (generational and incremental schemes), they may or may not guarantee the worst-case latency. Moreover, such schemes often prolong overall garbage collection time. In this paper, the performance analysis of the proposed Active Memory Module (AMM) for embedded systems is presented. Unlike the software counterparts, the AMM can perform a memory allocation in a predictable and bounded fashion (14 cycles). Moreover, it can also yield a bounded sweeping time regardless of the number of live objects or heap size. By utilizing the proposed system, the overall speedup can be as high as 23% compared to the garbage collection system of the JDK 1.2.2 running in classic mode.

OPERATING SYSTEMS TECHNIQUES FOR PARALLEL COMPUTATION IN INTELLIGENT MEMORY

Advances in DRAM density have led to several proposals to perform computation in memory [1] [2] [3]. Active Pages is a page-based model of intelligent memory that can exploit large amounts of parallel computation in data-intensive applications. With a simple VLIW processor embedded near each page on DRAM, Active Page memory systems achieve up to 1000X speedups over conventional memory systems [4]. Active Pages are specifically designed to support virtualized hardware resources. In this study, we examine operating system techniques that allow Active Page memories to share, or multiplex, embedded VLIW processors across multiple physical Active Pages. We explore the trade-off between individual page-processor performance and page-level multiplexing. We find that hardware costs of computational logic can be reduced from 31% of DRAM chip area to 12%, through multiplexing, without significant loss in performance. Furthermore, manufacturing defects that disable up to 50% of the page processors can be tolerated through efficient resource allocation and associative multiplexing.

Computer system, heal thyself

Researchers are accelerating work on self-monitoring, self-healing systems, which detect problems and continue to operate by fixing or simply bypassing malfunctions without human intervention. Although self-healing technology adds cost, the approach not only reduces potentially catastrophic delays or errors in critical systems but also saves money by reducing the need for IT department intervention. The article looks at the eLiza project and autonomic-computing projects from IBM including Active Memory system and Blue Gene project. The article also looks at ONE and N1 from Sun Microsystems, Hewlett-Packard's Superdome high-end Unix server and Blue Ocean Software's Track-It!.