Active Matrix Liquid Crystal Display Research Articles

Cd0.2Zn0.8O nanowire thin film transistor for low kickback high-speed AMLCD circuit applications

This paper reports the Cd0.2Zn0.8O channel cylindrical gate-all-around nanowire thin-film transistor (CY-GAA-NWTFT) for high-speed active-matrix liquid crystal display (AMLCD) pixel circuit with minimal kickback voltage. The AC/DC, analog, and energy efficiency of this device are investigated against the variation in lateral (channel length) as well as vertical dimension (oxide thickness) using technology computer aided design (TCAD) device simulation environment. Further, the behavior of CY-GAA-TFT is crosschecked by implementing it on resistive load digital inverter circuit followed by transient analysis to calculate delay of the inverter circuit. Moreover, static analysis has been also performed to evaluate its voltage transfer curve (VTC) to derive its noise margin and voltage gain. The execution of the proposed CY-GAA-NWT device on AMLCD pixel circuit indicates tremendous improvement in performance in terms of high-speed applications and low kickback voltage.

Enhancing Pixel Charging Efficiency by Optimizing Thin-Film Transistor Dimensions in Gate Driver Circuits for Active-Matrix Liquid Crystal Displays.

Flat panel displays are electronic displays that are thin and lightweight, making them ideal for use in a wide range of applications, from televisions and computer monitors to mobile devices and digital signage. The Thin-Film Transistor (TFT) layer is responsible for controlling the amount of light that passes through each pixel and is located behind the liquid crystal layer, enabling precise image control and high-quality display. As one of the important parameters to evaluate the display performance, the faster response time provides more frames in a second, which benefits many high-end applications, such as applications for playing games and watching movies. To further improve the response time, the single-pixel charging efficiency is investigated in this paper by optimizing the TFT dimensions in gate driver circuits in active-matrix liquid crystal displays. The accurate circuit simulation model is developed to minimize the signal's fall time (Tf) by optimizing the TFT width-to-length ratio. Our results show that using a driving TFT width of 6790 μm and a reset TFT width of 640 μm resulted in a minimum Tf of 2.6572 μs, corresponding to a maximum pixel charging ratio of 90.61275%. These findings demonstrate the effectiveness of our optimization strategy in enhancing pixel charging efficiency and improving display performance.

(Digital Presentation) Instability of α-Si:H TFTs under Simultaneous Ultraviolet Light Illumination and Different Bias Stresses

Hydrogenated amorphous silicon thin-film transistors (α-Si:H TFTs ) are widely applied in liquid crystal displays (LCD). They can be used as not only the switching devices in the panel but also the scan driving circuit in the active-matrix liquid crystal displays (AMLCD), as well as large-area optical imaging sensor arrays. The α-Si:H could be deposited on the glass or plastic substrates at the low temperature, good uniformity in the large area, and the process is relatively mature, so it is still a competitive material. This study would investigate the deterioration of the α-Si:H TFTs under various bias stressing conditions with and without UV light.For the DC bias stress on the gate terminal, the electron trapping within the gate dielectric under positive bias would cause the threshold voltage (Vth) to shift to the positive direction, but the hole trapping under negative bias would cause the Vth to shift to the negative one. Furthermore, under the DC bias stress, the UV light illuminates the TFTs simultaneously, and the active layer of TFTs would generate additional electrons and holes, which would increase the trapping probability of charges and the amount of degradation and recovery. Both effects of the electron capture in the dielectric and defects creation in the channel would cause the Vth to shift to the positive direction, so the degradation of TFTs under positive bias stress is relatively serious. The increment of the subthreshold swing of TFTs under negative bias stress would be much larger than those under positive one, and the captured holes are easily released in the reverse sweeping mode, leading to the decrease of the drain current. Therefore, the amount of degradation and recovery of the TFTs under negative bias stress is relatively small in the reverse sweeping mode, because the energy barrier of holes is smaller than that of electrons in the interface of α-Si:H/SiNx.For the experiments of AC bias stress on the gate terminal with UV light illuminating simultaneously, the frequency of AC signal is fixed at 10 KHz. It could be found that the leakage current in the cut-off region under negative bias (-35 ~ 0 V) stress would increase with the stress time lasting, which shows that the holes are trapped within the gate dielectric closer to the active layer at the high frequency. These shallow positive trapped charges would attract the electrons to accumulate in the channel region, which causes the drain current to increase gradually. However, under bipolar bias (-17.5 ~ +17.5 V) stress, the charge trapping would first dominate the Vth degradation of TFTs, and then the defect states creation would gradually dominate the change of the Vth as the stress time increasing, which causes the Vth first to shift to the negative direction and then to positive one.For another experiments of AC bias stress on the gate terminal without UV light illumination, the frequencies of AC signals are fixed at 10 Hz and 10 KHz with different ranges of biasing voltages. It could be found that the Vth degradation of TFTs at different frequencies under the higher positive bias cycle (0 ~ +35 and -10 ~ +25 V) is not obviously different, mainly because the speed of electron’s accumulation and disappearance in the channel region could keep up with the switching speed of AC signals. However, it could be found that during the higher negative bias cycle(-35 ~ 0 and -25 ~ +10 V), the amount of change in the Vth at low frequency is relatively larger than that at high frequency, which is due to the RC delay effect of the n+α-Si:H layer on the holes under negative bias stress. To investigate the recovery behavior of TFTs, including the direction and amount of the Vth change in the resting time, we could know the dominating mechanism that leads to the TFT’s degradation. And the probably balanced AC bias stress condition is about -10 ~ +25 V. As the magnitude of negative biasing voltage increases, the holes capture within the gate dielectric would increase, and the drain current in the cut-off region also increases.Finally, the β parameter, in the formula of ΔVth= Atβ, is obtained by fitting the trends of ΔVth v.s. stress times. The value of β parameter would exhibits the influence of different mechanisms on the degradation of TFTs stressed by different bias conditions and with/without UV light illumination over the stressing time. And these results are consistent with above experimental data.

Thin-Film Transistors

Thin film transistors (TFTs) are key components used in a variety of fields such as solar cell, active-matrix liquid crystal displays (AM-LCDs), pixel switches, peripheral driver circuit and flexible electronics [...]

The 60th Anniversary of TFTs and the Evolution of High‐Resolution Displays

The 60th Anniversary of TFTs and the Evolution of High‐Resolution Displays

IEEE Open Journal of the Solid-State Circuits Society Special Section on Integrated Circuits and Systems Based on Thin-Film Transistors

Thin-Film transistors (TFTs) are ubiquitous today as a backplane technology for various display and imager products. Those transistors act as switches in active-matrix liquid-crystal displays (AM-LCDs) or as full-pixel engines, including driving and threshold compensation, in active-matrix organic light-emitting diodes (AM-OLEDs) panels. TFT manufacturing requires only a limited amount of photolithographic steps, making it a relatively simple transistor technology, compared to the traditional Si CMOS technologies. The processing temperature of TFT technologies is sufficiently low to be compatible with glass and can even enable flexible substrates. Finally, these transistors have been developed specifically for large-area applications, such as televisions and X-ray scanners. Consequently, the backplane size for TFTs has evolved from the generation-1 glass panel of 270 mm by 360 mm to generation-10.5, which is manufactured on a glass panel of 2.94 m <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times3.37$ </tex-math></inline-formula> m <xref ref-type="bibr" rid="ref1" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[1]</xref> . This is profoundly different from traditional Si CMOS integrated circuits, which are fabricated nowadays on 200 mm or 300 mm round wafers. The critical dimension of the TFT technology on glass or flexible substrate in production is in the range of a few micrometers. The TFT research in the display field focuses on enabling increasingly better pixel resolution, improved visual quality, larger panels for LED walls, flexible displays, camera-behind display, sensor integration, and many more.

Subjective measurement of the Stiles-Crawford effect with different field sizes.

The Stiles-Crawford effect of the first kind (SCE) is the phenomenon in which light entering the eye near the center of the pupil appears brighter than light entering near the edge. Previous investigations have found an increase in the directionality (steepness) of the effect as the testing location moves from the center of the visual field to parafoveal positions, but the effect of central field size has not been considered. The influence of field size on the SCE was investigated using a uniaxial Maxwellian system in which stimulus presentation was controlled by an active-matrix liquid crystal display. SCE directionality increased as field size increased from 0.5° to 4.7° diameter, although this was noted in four mild myopes and not in two emmetropes. The change with field size was supported by a geometric optics absorption model.

Building a Display Field Leader: SKL's Journey

Building a Display Field Leader: SKL's Journey

Kopin Hits OLED Microdisplay Milestone

MICRODISPLAY SUPPLIER KOPIN CORPORATION—which specializes in wearable headset products for the military, industrial, enterprise, and consumer markets—says it shipped the first production order of its 720p color OLED microdisplays to a US company for public safety applications. The 0.49-in.-diagonal 720p display uses the combination of Kopin's proprietary ColorMax technology for superior color fidelity and a duo-stack OLED structure (which is essentially two layers of OLEDs) for high current efficiency and low power consumption. Kopin makes microdisplays used in everything from helmet displays for fighter jets to smart glasses for running and cycling. It has historically manufactured its own active-matrix LCD and liquid crystal on silicon (LCOS) displays, but it is pursuing a fabless model for its OLED products. The 720p-color OLEDs are made by the Chinese firm Lakeside Optoelectronic Technology at its factory in Changzhou, China. “We are very pleased with our first production order of our color duo-stack 720 OLED microdisplays, which is for a product made by a US company,” John C.C. Fan, CEO of Kopin, says in a press release. “Though this initial order is fairly modest in size, it is an important milestone for our OLED microdisplay business, and is a true proof-point of our fabless OLED display business model in which our OLED partner, Lakeside, manufactures the displays on our ColorMax backplane wafers to meet our specifications. With the successful production of duo-stack color displays on our ColorMax wafers, we believe it will be the first of many orders from companies around the world that want to leverage our industry-leading technology.” Kopin's color display is made with a duo-stack white OLED structure and color filters. The company's patent-pending ColorMax technology uses a specially configured anode structure in the silicone backplane to suppress color mixing among tiny subpixels (2.8 × 8.4 micrometers in the 720p display), which be problematic would otherwise in duo-stack OLED structures. Duo-stack is Kopin's strategy to improve luminance, a long-time challenge in using OLED microdisplays for augmented reality applications, says Guillaume Chansin, director of display research for Display Supply Chain Consultants. “When you're going to overlap an image in front of the reality, you want that image to be bright enough so you can see it, especially in bright daylight,” Chansin says. “The OLED technology that has been available so far was not bright enough, so now what companies like Kopin are doing is to find ways to push the brightness up.” Other microdisplay firms are taking different approaches, such as Hopewell Junction, New York-based eMagin Corporation, which uses a technique called direct patterning in its OLEDs that produces red, green, and blue (RGB) light without requiring a color filter. Both Kopin and eMagin have achieved more than 7,000 nits with their OLED microdisplays. Chansin says it remains unclear, though, which technical approach is superior for mass-market consumer devices. He notes that Sony is also a big player in OLED microdisplays, but it has yet to disclose a particular strategy for improving brightness. “It's really hard to tell at this point, because this problem has been around for quite a long time and a lot of people have come out with ideas to do a brighter OLED,” Chansin says. “But we still don't know what the limit is. Both companies [Kopin and eMagin] say they want to go to something like 30,000 nits eventually.” In the near term, other opportunities exist for OLED microdisplays in virtual reality (VR) headsets, where brightness may not be as much of a key requirement. Kopin has already worked with Panasonic to produce micro-OLED panels for prototype ultra-high definition (UHD) VR goggles. The 1.3-in. panels, which feature high dynamic range and 2.6K (2,560 × 2,560) resolution, work in combination with 3M's Pancake optics to create a lightweight goggle suitable for VR sports or entertainment applications. —Glen Dickson Kopin's Microdisplay A 0.49-in. diagonal 720p OLED display incorporating ColorMax technology. source: Kopin

(Invited) Atomic Layer Deposited Amorphous Igzo Semiconductor with Vertical Composition Engineering for High Mobility Field Effect Transistor

Amorphous oxide semiconductors have been widely studied for the potential use in flat-panel displays such as active matrix liquid crystal display (LCD) and Organic light emitting didoes (OLEDs). Since reporting amorphous InGaZnO semiconductor thin film transistor (TFT) in 2003 & 2004, many multi-component oxide semiconductors have been intensively investigated and developed by physical vapor deposition (PVD) method. Very recently, the sputtered InGaZnO TFTs are already adopted in mass-production to fabricate AMOLED TVs. Also, semiconductor industries have looked at metal oxide semiconductor thin films as an alternative Si channel layer because this semiconductor exhibited extremely low-off current level (below 10-18A/um). It is the unique property to decrease power consumption for various semiconductor devices. However, there remain several problems such as enhancing field effect mobility, composition uniformity, bias-temperature stability, and p-type oxide semiconductor in order to go further for the future device applications.In this talk, I will introduce various oxide semiconductor materials with atomic layer deposition (ALD) methods. Unlike PVD, ALD method has unique properties, including controlling atomic-level-thickness, manipulating atomic-level-composition control, and depositing impurity-free & uniform films. The key materials such In2O3, ZnO, SnO2, and Ga2O3 will be summarized and then I will show the combinatorial research works in terms of amorphous InGaZnO semiconductor thin film transistors. Generally, electrical properties of amorphous oxide semiconductors are strongly dependent on each element composition. The indium (In) rich InGaZnO exhibited a high mobility of 50cm2/V.sec. However, the In-rich InGaZnO TFTs have the demerit of negative threshold voltage owing to intrinsically high carrier density. I will present that In-rich IGZO TFTs with vertical stacked InOx, ZnOx and GaOx atomic layers show excellent performances such as saturation mobility of ~ 74cm cm2/V.sec, threshold voltage of -1.3V, on/off ratio of 8.9 × 108, subthreshold swing of 0.26V/decade, and hysteresis of 0.2V, while keeping a reasonable carrier density of ~1017 cm-3. Flexible ALD InGaZnO TFTs on polymer substrates were also discussed depending on gate insulator materials, in terms of device performances. ALD technique will be a very promising candidate to improve oxide semiconductor materials as well as various device applications (Display & Semiconductor Industry) because it has not only unique nano-growth mechanism but also ultimate uniform property.

TCAD Simulation of the Electrical Characteristics of Polycrystalline Silicon Thin Film Transistor

&#x0D; Low-temperature polycrystalline silicon thin film transistors (poly-Si TFTs) have been studied because of their high performance in Active Matrix Liquid Crystal Displays (AMLCD's) and Active Matrix Organic Light-Emitting Diode (AMOLED) applications. The purpose of this work is to simulate the impact of varying the electrical and physical parameters (the interface states, active layer's thickness and BBT model) in the transfer characteristics of poly-Si TFT to extract the electrical parameters like the threshold voltage, the mobility and to evaluate the device performance. The device was simulated using ATLAS software from Silvaco, the results show that the electrical and physical parameters of poly-Si TFT affect significantly its transfer characteristics, choosing suitable parameters improve high-performance transistor. Such results make the designed structure a promising element for large-scale electronics applications.&#x0D; &#x0D; &#x0D;

High performance of solution-processed SnO2 thin-film transistors by promotion of photo-exposure time-dependent carrier transport during the pre-annealing stage

We fabricate high-performance solution-processed SnO2 thin-film transistors (TFTs) exhibiting improved carrier transport features by exposing the ultraviolet/ozone (UV/O3) on the SnO2 film during the pre-annealing stage. The SnO2 layer is treated with different UV/O3-exposure times from 0 to 60 minutes before the post-annealing step. As UV/O3-exposure time increases from 0 to 30 minutes, the M-O-M (M, metal; and O, oxygen) network, mass density, and oxygen vacancies of films are enhanced. In contrast, the M-O-M network and mass density decrease, while the oxygen vacancies rather increase when the UV/O3-exposure time reaches 60 minutes beyond 30 minutes. The SnO2 (Sn4+) phase, thickness, and surface morphology of SnO2 films are not considerably changed regardless of UV/O3-exposure time. When the UV/O3-exposure time is 30 minutes, devices demonstrate superior field-effect mobility (10.1 cm2 V−1 s−1) at approximately two times higher than the TFT without UV/O3-exposure. Furthermore, the SnO2 TFT with UV/O3-exposure time for 30 minutes shows improved subthreshold-swing characteristics and a high on/off current ratio. These devices are adequate for use in high-resolution active-matrix LCDs or OLED displays that demand a high field-effect mobility (>10 cm2 V−1 s−1) and on/off ratio (>106).

An Area and Power Efficient Interpolation Scheme Using Variable Current Control for 10-Bit Data Drivers in Mobile Active-Matrix LCDs

This paper presents an area and power efficient interpolation scheme using variable current control (VCC) for 10-bit data drivers in mobile active-matrix LCDs. The VCC interpolation can be embedded in buffer amplifiers as sub-digital-to-analog converters (DACs), reducing the DAC area without requiring additional power and conversion time. Moreover, interpolation errors due to transistor nonlinearity can be compensated through delicate current ratio control, optimizing both accuracy and area efficiency of the high-resolution data driver. The prototype 10-bit data driver with a 6-bit resistor DAC and a 4-bit interpolation sub-DAC occupies the chip area of 460 ${\mu }{\text{m}}\,\,{\times }$ 14 ${\mu }{\text{m}}$ per channel, which is 10.7% smaller than the conventional 8-bit data driver. The data driver consumes static current of 1 ${\mu }\text{A}$ /channel without dissipating additional power for interpolation. The measured integral nonlinearity and differential nonlinearity are 0.4 LSB and 0.7 LSB, respectively. The proposed scheme has competitive performance in terms of driving accuracy, chip size shrinkage, and static power consumption for high-resolution data drivers.

Survey on Single Stage Amplifiers for Column Drivers in Active Matrix LCD Panels Leading to a Highly Linear Rail-to-Rail Robust Amplifier

This paper reviews single stage amplifiers identified in the literature as well as presents a new structure single stage highly linear rail-to-rail amplifier intended for column drivers in Active Matrix Liquid Crystal Display (AMLCD). The new proposed amplifier is based on applying current splitting technique on a rail-to-rail differential pair thus elevating the overall performance of the amplifier in terms of different performance parameters such as effective transconductance, output resistance, DC gain and unity gain frequency among others. One major advantage of the new proposed amplifier is its capability of providing a rail-to-rail stable operation without the need for compensation. The performance of the new proposed amplifier is tested on LTspice using 90nm CMOS technology under 1 Volts supply voltage and compared to other existing single stage amplifiers. Simulation results shows that the proposed amplifier provides a high DC gain, high effective transconductance and high output resistance while maintaining a stable operation with a phase margin of 80°. Obtained results also confirms that the amplifier exhibits rail-to-rail operation while maintaining a very low Total Harmonic Distortion (THD). The pulse response of the proposed amplifier indicates a fast response with a rise time and fall times almost twice as fast as the other examined topologies. Against Process, Voltage and Temperature (PVT) variations, the amplifier exhibits a robust performance as the DC gain variation range was within 20% only which is much less than the other examined topologies.

Amendment of CIECAM02 with a technical extension to compensate Helmholtz-Kohlrausch effect for chromatic characterization of display devices

This paper proposes a method of compensating for the Helmholtz-Kohlrausch (H-K) effect which is a factor not being concerned in CIECAM02. H-K effect refers to the color appearance phenomenon that colored light appears brighter than achromatic light of the same luminance. By the magnitude estimation method, the perceptual lightness of active matrix liquid crystal display (AMLCD) is investigated. The results show that the lightness values predicted by CIECAM02 are lower than perceptual lightness values evaluated by the psychophysical experiments because of the H-K effect. The results on MobileCAM-v2, which is a refined version of CIECAM02, are investigated, as well. Since the color gamut of the display has been widening, the compensation for the H-K effect has also been increasingly important. In this paper, the method to compensate for the H-K effect in CIECAM02 is proposed. By modifying Fairchild’s equation, which is previously announced for CIELAB, CIECAM02 can be developed as a more complete color appearance model that can be universally applied to the display devices having a wide color gamut.

Vertical Channel a-IGZO Thin Film Transistors Using Thin Gate Dielectric

Oxide thin film transistors (TFTs) are widely used as backplane for displays such as active matrix organic light emitting diode display and active matrix liquid crystal display. And also, it can be used in many applications such as sensor and wearable devices which require small power consumption. For low power consumption, the operation voltage should be decreased and the vertical structure TFT is a candidate due to short channel length. In this study, we proposed a vertical structure TFTs using a thin gate dielectric. In this experiment, a vertical structure TFTs with a channel formed on the vertical sidewall of the gate electrode and a channel length controlled by the thickness of the gate electrode is proposed. The channel length was adjusted by the thickness of the gate electrode in the vertical TFTs developed in this paper. Figure 1 shows the fabricated vertical a-IGZO TFT developed in this study. This vertical TFTs has the feature of controlling the channel length by the thickness of the gate electrode and can achieve short channel length easily, which is useful for low driving voltage. To reduce the gate voltage also, the thin gate dielectric was used. Since the very thin gate insulator was used, low threshold voltage was obtained, and low voltage driving was possible. Figure 1

Bottom-Metal Induced Leakage Current of LTPS Diode for ESD Protection

Leakage current behavior was investigated for diode-connected LTPS TFTs (LTPS diode) for electrostatic discharge (ESD) protection in display product with high luminance backlight system. In this study, the bottom metal layer was adopted to suppress leakage current caused by light coming from backlight system. Different off-current behavior as each other electrical connection of metal layer was observed, source-contacted or floating bottom metal showed the high leakage current by increasing current flow through back-channel at off states while gate-contacted bottom metal have comparable low leakage current with non-bottom metal layer. This leakage current characteristic was verified by technology computer-aided design (TCAD) simulation. Objectives and Background A low temperature polycrystalline silicon (LTPS) have been widely used for in active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting diode displays (AMOLEDs) as thin film transistor (TFT) backplane and system on panel (SOP), combined with controller, memory, and driver circuits, due to excellent electrical characteristics. The LTPS TFT based displays can achieve high brightness, high aperture ratio, high resolution, and low power consumption due to excellent electrical characteristics. On the other hand, in display product with high luminance backlight system, such as auto and mobile products, the LTPS TFTs require a bottom metal layer to reduce leakage current caused by light coming from backlight unit (BLU). This bottom metal layer in contacted with gate or source electrodes is applied under the poly-Si layer. However, this bottom metal layer may also affect seriously the leakage current of diode-connected LTPS TFTs (LTPS diode) for electrostatic discharge (ESD) protection in SOP. In this study, the leakage current of LTPS diode for ESD protection was investigated with gate-contacted bottom metal, source-contacted bottom metal, and floating bottom metal compared with non-bottom metal. We measured the electrical characteristics with variation of electrical connection of bottom metal layer. Also, the technology computer-aided design (TCAD) simulation was performed to analyze the physical mechanism. From analysis results, optimized bottom metal design of LTPS diode was proposed for ESD production. Experiment Figure 1 shows the top-gate coplanar n-channel LTPS TFT structure with bottom metal layer under poly-Si. Gate and Drain electrodes were connected to common electrode in LTPS TFTs structure for LTPS diode. This LTPS diode was fabricated at low temperature of less than 450°C on glass substrate. The standard commercial NMOS processes, including the ion implantation, the excimer laser annealing (ELA), and the rapid thermal annealing (RTA), were employed in this experiment. To observe the electrical characteristics of LTPS diode, I-V characteristics were measured by using an Agilent B1500A semiconductor analyzer at room temperature. Results and Discussion Figure 2 shows I-V characteristics of LTPS diodes with gate-contacted bottom metal, source-contacted bottom metal, and floating bottom metal compared with non-bottom metal. The leakage current with source-contacted and floating bottom metal increased considerably compared with non-bottom metal. Especially, the leakage current with source-contacted bottom metal increased more than with floating bottom metal. On the other hand, the leakage current with gate-contacted bottom metal was low enough to be comparable with non-bottom metal. To analyze this phenomenon, we observed the electron concentration distribution within poly-Si at VGS= 0V, 10V, and -10V region using technology computer-aided design (TCAD) simulation as shown figure 3. For source-contacted bottom metal and floating bottom metal, at VGS= -10V, the electron was accumulated in the back-channel of poly-Si since the positive voltage is applied to back-channel by voltage difference between drain and bottom metal even though drain (=gate) electrode is applied to negative voltage. Therefore, at VGS= -10V, the leakage current flows through the back-channel in LTPS diodes with source-contacted bottom metal and floating bottom metal. But, for LTPS diode with gate-contacted bottom metal, when drain electrode was applied to negative voltage, there is no different voltage bottom metal and gate electrode because these electrodes were linked in common. Therefore, LTPS diode with gate-contacted bottom metal has low leakage current as comparable with non-bottom metal. Conclusion In summary, the leakage current of LTPS diode was strongly dependent on electrical connection of bottom metal layer. The electrical connection of bottom metal affects back-channel region within poly-Si due to the difference between bottom metal and drain electrodes at off region. Especially, LTPS diode with source-contacted bottom metal and floating bottom metal increased considerably the leakage current, while, gate-contacted bottom metal decreased leakage current. Therefore, bottom metal layer should be connected by gate electrode in LTPS diode for ESD protection. Figure 1

アクティブマトリクス型液晶表示パネルにおける「焼き付き」の定量評価

アクティブマトリクス型液晶表示パネルにおける「焼き付き」の定量評価

High‐Resolution LCD Headlamps for Intelligent Lighting

Vehicle headlamps that adapt to external conditions are established and available in mass‐production vehicles; now the market is requesting headlamp systems with increasing resolution. Active‐matrix LCD (AMLCD) with amorphous silicon thin‐film transistors (a‐Si TFTs) is a mature and cost‐efficient technology that is known for its reproducible and homogeneous performance. Integrating an AMLCD with a‐Si TFTs into an LED‐based headlamp can fulfill all specifications for realizing a fully adaptive headlamp setup with high resolution.

Time-dependent color simulation of active-matrix liquid crystal display adopting the field sequential driving method

A time-dependent display color simulation method is proposed. For the time-dependent simulation, we applied our behavioral model of liquid crystals (LC). The model provides the transient response characteristics of the LC. The color simulation of a twisted nematic active matrix liquid crystal display (AMLCD) adopting a field sequential (FS) driving method is possible when combining the transient LC responses with periodically operating red-greenblue (RGB) light emitting diodes (LEDs). By modifying the gate start pulse of the conventional AMLCD, we created a virtual AMLCD driven by the FS method. The color performance of the panel was measured at five vertical positions, and the results showed that the RGB LEDs should be driven by a 70% duty parameter and a 50% shifting parameter to minimize line-to-line color characteristic deviations in the AMLCD panel. By using the proposed simulation method, it is possible to find the optimal FS driving condition for any display with arbitrary response characteristics to exhibit the best color performance.