Active Load Circuit Research Articles

Dual-mode power reduction technique for real-time image and video processing board

In real-time image and video processing boards, power, speed, and area are the most often used measures for determining the performance of motion imagery applications. Due to technological advancement, power consumption has gained major attention in real-time image processing ability compared to speed. The increase in on-chip temperature due to larger power consumption has resulted in reduced operating life of chip and battery-driven devices. In this work, a new logic family has been introduced i.e., dual-mode logic (DML), which provides flexibility between the optimization of energy and delay (E-D optimization). This gate can be switched between two modes of operation that is a static mode (CMOS-like mode), which provides low power consumption and dynamic mode, which provides high speed. Recently, power leakage has become a dominant problem due to continuous data transfer among a large number of connected devices. Thus, to reduce power leakage, a self-controllable voltage level (SVL) power reduction technique is used along with DML logic. In the SVL technique, a maximum dc voltage is provided to the active load circuit on-demand or decrease the dc supplied to the load circuit in the standby mode. Integrating DML with the SVL technique reduces power consumption as well as leakage power. A 4-bit RCA, 8-bit RCA, and 16-bit RCA are used for verifying the proposed method and comparison of performance parameters is done with a conventional circuit. Complete circuit implementation and simulation are carried out in TANNER EDA version 13 tools with operating voltage of 1 V. The proposed system is further applied to real-time image, and we obtain the finest resolution level with minimum power consumption.

A Sub-1 V nanopower subthreshold current and voltage reference using current subtraction technique and cascoded active load

A sub-1 V, subthreshold current and voltage references are presented using Cascaded Current Mirrors (CCM) as temperature compensator and cascoded transistors as active load. The CCM uses current subtraction concept for temperature compensation of supply independent current generated from Current Generator Circuit (CGC) giving rise to reference current which is fed to active load circuit (ALC). The ALC consists of cascoded PTAT and CTAT voltages to generate supply and temperature independent output reference voltage. The proposed references are implemented and simulated in Cadence Virtuoso using 180 nm CMOS technology model for 0.95–1.8 V supply voltage range. The average output reference voltage of 609.7 mV is obtained with the line regulation of 1.99 mV/V. The supply current of 60.7 nA is found at 0.95 V supply along with Temperature Coefficient (TC) of 44.5 ppm/°C for a temperature range of −20 to 108 °C. A high-value PSRR of −42 dB at 100 Hz and −17 dB at 1 MHz is achieved. It has an area of 0.0082 mm2. The obtained average reference current is 6 nA having a slope of 5.5pA/°C.

A Low Power Low Supply MOS-Only Subthreshold Voltage Reference for Wide Temperature Range

A Sub-1V, MOS-only Voltage Reference Circuit (VRC) has been proposed with the utmost of transistors working as subthreshold region for low-supply and low-power applications. A supply-insensitive current is passed to Active Load Circuit (ALC) for supply and temperature independence at the output reference voltage. It has four current mirrors connected in a closed loop configuration to generate a supply-independent current which is passed through the ALC resulting supply and temperature insensitive output reference voltage. The ALC has a combination of two subthreshold NMOS transistors having different threshold voltages. The presented VRC is simulated using standard 90 nm CMOS model for 0.25-1 V supply voltage range. The simulation result gives minimum operating voltage required as 0.25 V for which all transistors work in their respective region of operation. For the supply range of 0.25-1 V, the obtained mean voltage reference is 100.4 mV with the line regulation of 0.186 mV/V. The temperature coefficient (TC) of 51ppm/°C is achieved for a wide temperature range of -50 to 135°C with the given minimal operating supply voltage. The power dissipation for minimal supply voltage at room temperature is 33 nW. The proposed VRC exhibits a high PSRR of -52.5 dB at 100Hz and -29 dB at 1 MHz.

A Low-Power, Sub-1-V All-MOSFET Subthreshold Voltage Reference Using Body Biasing

A low-voltage and low-power all-MOSFET voltage reference is presented having most of the transistors working in subthreshold region. The basic beta-multiplier with cascode transistor provides a supply-independent current utilized by the active load circuit to generate an output reference voltage using body biasing. The proposed circuit is simulated using standard SCL 180-nm CMOS technology for the supply voltage ranging from 0.75[Formula: see text]V to 1.8[Formula: see text]V. The simulation obtains an average output voltage reference of 450.4[Formula: see text]mV for the given supply range at room temperature. The minimum power dissipation at room temperature is 54.37[Formula: see text]nW. The temperature coefficient (TC) of 28.13[Formula: see text]ppm/∘C is achieved having the temperature range of [Formula: see text]10–87∘C for the minimum operating supply voltage. It has the PSRR values of [Formula: see text]39.4[Formula: see text]dB at 100[Formula: see text]Hz and [Formula: see text]12[Formula: see text]dB at 1[Formula: see text]MHz. Also, the active area of the proposed circuit is 0.014[Formula: see text]mm2.

Design of Low Leakage Current Average Power CMOS Current Comparator Using SVL Technique With Pseudo NMOS and Transmission Gate Logics

Abstract Comparatorare most widely used second electronic components after operational amplifier. For ADC circuit we have to use the high speed and low power consumption based comparator. SVL circuit is used tom reduce the offset voltage which requires high voltage gain. A SVL circuit can supply maximum DC voltage to an active load circuit on request or can decrease the DC voltage supplied to a load circuit in the standby mode was developed. SVL circuit is used with comparator which reduce the power consumption from 258.6μw to 156.7μw. Pseudo nmos logic and transmission gate logic is used with the SVL based current comparator which further reduce the power consumption in the standby mode. This technique based comparator is fabricated on the tanner tool of 45nm technology.SVL technique is mostly recommended for CMOS logic.