Accurate Hardware Research Articles

Design of a low-area hardware architecture to predict early signs of sudden cardiac arrests

Sudden cardiac arrest (SCA) results in an unexpected and untimely death within minutes, and its early prediction can alert cardiac patients to a timely medical diagnosis. To detect early symptoms of an SCA, the detection and classification of ventricular tachycardias (VT) are of utmost importance. In this work, a low-area yet highly accurate hardware architecture for VT classification is proposed based on the detection of premature ventricular contraction (PVC) beats. After pre-processing of the ECG signals using a wavelet-based pre-processing unit, a characteristics-matching algorithm is used to detect the PVC beats, and a low-complexity adaptive decision-based logic classifier is used to classify them into four types of VTs, namely monomorphic, polymorphic, non-sustained VT (NSVT), and sustained VT (SVT). FPGA verification of the hardware architecture for the VT classifier using the Nexys 4 DDR Artix-7 board utilizes 10.4 % of the total available resources and displays the type of VT and the number of PVCs detected to help in determining the severity of SCA and the need for medical attention. The ASIC implementation of the proposed PVC-based VT classification using the SCL 180 nm CMOS technology results in an area overhead of 0.02 mm2 and a power consumption of 3.47 μW for a high accuracy rate of 98.2 %. When compared to the existing CA detection systems for wearable devices, the proposed one consumes the least area while achieving high detection rates.

Dynamic Modelling, Process Control, and Monitoring of Selected Biological and Advanced Oxidation Processes for Wastewater Treatment: A Review of Recent Developments.

This review emphasizes the significance of formulating control strategies for biological and advanced oxidation process (AOP)-based wastewater treatment systems. The aim is to guarantee that the effluent quality continuously aligns with environmental regulations while operating costs are minimized. It highlights the significance of understanding the dynamic behaviour of the process in developing effective control schemes. The most common process control strategies in wastewater treatment plants (WWTPs) are explained and listed. It is emphasized that the proper control scheme should be selected based on the process dynamic behaviour and control goal. This study further discusses the challenges associated with the control of wastewater treatment processes, including inadequacies in developed models, the limitations of most control strategies to the simulation stage, the imperative requirement for real-time data, and the financial and technical intricacies associated with implementing advanced controller hardware. It is discussed that the necessity of the availability of real-time data to achieve reliable control can be achieved by implementing proper, accurate hardware sensors in suitable locations of the process or by developing and implementing soft sensors. This study recommends further investigation on available actuators and the criteria for choosing the most appropriate one to achieve robust and reliable control in WWTPs, especially for biological and AOP-based treatment approaches.

Digital design of a spatial-pow-STDP learning block with high accuracy utilizing pow CORDIC for large-scale image classifier spatiotemporal SNN

The paramount concern of highly accurate energy-efficient computing in machines with significant cognitive capabilities aims to enhance the accuracy and efficiency of bio-inspired Spiking Neural Networks (SNNs). This paper addresses this main objective by introducing a novel spatial power spike-timing-dependent plasticity (Spatial-Pow-STDP) learning rule as a digital block with high accuracy in a bio-inspired SNN model. Motivated by the demand for precise and accelerated computation that reduces high-cost resources in neural network applications, this paper presents a methodology based on COordinate Rotation DIgital Computer (CORDIC) definitions. The proposed designs of CORDIC algorithms for exponential (Exp CORDIC), natural logarithm (Ln CORDIC), and arbitrary power function (Pow CORDIC) are meticulously detailed and evaluated to ensure optimal acceleration and accuracy, which respectively show average errors near 10–9, 10–6, and 10–5 with 4, 4, and 6 iterations. The engineered architectures for the Exp, Ln, and Pow CORDIC implementations are illustrated and assessed, showcasing the efficiency achieved through high frequency, leading to the introduction of a Spatial-Pow-STDP learning block design based on Pow CORDIC that facilitates efficient and accurate hardware computation with 6.93 × 10–3 average error with 9 iterations. The proposed learning mechanism integrates this structure into a large-scale spatiotemporal SNN consisting of three layers with reduced hyper-parameters, enabling unsupervised training in an event-based paradigm using excitatory and inhibitory synapses. As a result, the application of the developed methodology and equations in the computational SNN model for image classification reveals superior accuracy and convergence speed compared to existing spiking networks by achieving up to 97.5%, 97.6%, 93.4%, and 93% accuracy, respectively, when trained on the MNIST, EMNIST digits, EMNIST letters, and CIFAR10 datasets with 6, 2, 2, and 6 training epochs.

LOCATOR: Low-power ORB accelerator for autonomous cars

Simultaneous Localization And Mapping (SLAM) is crucial for autonomous navigation. ORB-SLAM is a state-of-the-art Visual SLAM system based on cameras used for self-driving cars. In this paper, we propose a high-performance, energy-efficient, and functionally accurate hardware accelerator for ORB-SLAM, focusing on its most time-consuming stage: Oriented FAST and Rotated BRIEF (ORB) feature extraction. The Rotated BRIEF (rBRIEF) descriptor generation is the main bottleneck in ORB computation, as it exhibits highly irregular access patterns to local on-chip memories causing a high-performance penalty due to bank conflicts. We introduce a technique to find an optimal static pattern to perform parallel accesses to banks based on a genetic algorithm. Furthermore, we propose the combination of an rBRIEF pixel duplication cache, selective ports replication, and pipelining to reduce latency without compromising cost. The accelerator achieves a reduction in energy consumption of 14597× and 9609×, with respect to high-end CPU and GPU platforms, respectively.

A Fast, Accurate, and Comprehensive PPA Estimation of Convolutional Hardware Accelerators

Convolutional Neural Networks (CNN) are widely adopted for Machine Learning (ML) tasks, such as classification and computer vision. GPUs became the reference platforms for both training and inference phases of CNNs due to their tailored architecture to the CNN operators. However, GPUs are power-hungry architectures. A path to enable the deployment of CNNs in energy-constrained devices is adopting hardware accelerators for the inference phase. However, the literature presents gaps regarding analyses and comparisons of these accelerators to evaluate Power-Performance-Area (PPA) trade-offs. Typically, the literature estimates PPA from the number of executed operations during the inference phase, such as the number of MACs, which may not be a good proxy for PPA. Thus, it is necessary to deliver accurate hardware estimations, enabling design space exploration (DSE) to deploy CNNs according to the design constraints. This work proposes a fast and accurate DSE approach for CNNs using an analytical model fitted from the physical synthesis of hardware accelerators. The model is integrated with CNN frameworks, like TensorFlow, to generate accurate results. The analytic model estimates area, performance, power, energy, and memory accesses. The observed average error comparing the analytical model to the data obtained from the physical synthesis is smaller than 7%.

Forming‐Free Resistive Switching Memory Crosspoint Arrays for In‐Memory Machine Learning

In‐memory computing (IMC) with crosspoint arrays of resistive switching memory (RRAM) has gained wide attention for accelerating machine learning, data analysis, and deep neural networks. By IMC, matrix‐vector multiplication (MVM) can be executed in the crosspoint array in just one step, thus accelerating a broad range of tasks in machine learning and data analytics. However, a key issue for RRAM crosspoint arrays is the forming operation of the memories which limits the stability and accuracy of the conductance state in the memory device. In this work, a hardware implementation of crosspoint array of forming‐free devices for fast, energy‐efficient accelerators of MVM is reported. RRAM devices with a 1.5 nm‐thick HfO2 layer show an initial low resistance without forming and an analogue‐mode programming behavior for high‐accuracy IMC. Accurate hardware MVM is demonstrated by experimental eigenvalue/eigenvector calculation according to the power‐iteration algorithm, with a fast convergence within about ten iterations to the correct solution. Deflation technique and principal component analysis (PCA) enable the classification of the Iris dataset with 98% accuracy compared with floating‐point implementation. These results support forming‐free crosspoint arrays for accelerating advanced machine learning with IMC.

A Novel Method for Scalable VLSI Implementation of Hyperbolic Tangent Function

Hyperbolic tangent and Sigmoid functions are used as non-linear activation units in the artificial and deep neural networks. Since, these networks are computationally expensive, customized accelerators are designed for achieving the required performance at lower cost and power. The activation function and MAC units are the key building blocks of these neural networks. A low complexity and accurate hardware implementation of the activation function is required to meet the performance and area targets of such neural network accelerators. Moreover, a scalable implementation is required as the recent studies show that the DNNs may use different precision in different layers. This paper presents a novel method based on trigonometric expansion properties of the hyperbolic function for hardware implementation which can be easily tuned for different accuracy and precision requirements.

A High-Level Modeling Framework for Estimating Hardware Metrics of CNN Accelerators

GPUs became the reference platform for both training and inference phases of Convolutional Neural Networks (CNN) due to their tailored architecture to the CNN operators. However, GPUs are power-hungry architectures. A path to enable the deployment of CNNs in energy-constrained devices is adopting hardware accelerators for the inference phase. The design space exploration of CNNs using standard approaches, such as RTL, is limited due to their complexity. Thus, designers need frameworks enabling design space exploration that delivers accurate hardware estimation metrics to deploy CNNs. This work proposes a framework to explore CNNs design space, providing power, performance, and area (PPA) estimations. The heart of the framework is a system simulator. The system simulator front-end is TensorFlow, and the back-end is performance estimations obtained from the physical synthesis of hardware accelerators, not only from components like multipliers and adders. The first set of results evaluate the CNN accuracy using integer quantization, the accelerators PPA after physical synthesis, and the benefits of using a system simulator. These results allow a rich design space exploration, enabling selecting the best set of CNN parameters to meet the design constraints.

A Non-Intrusive Tool Chain to Optimize MPSoC End-to-End Systems

Multi-core systems are now found in many electronic devices. But does current software design fully leverage their capabilities? The complexity of the hardware and software stacks in these platforms requires software optimization with end-to-end knowledge of the system. To optimize software performance, we must have accurate information about system behavior and time losses. Standard monitoring engines impose tradeoffs on profiling tools, making it impossible to reconcile all the expected requirements: accurate hardware views, fine-grain measurements, speed, and so on. Subsequently, new approaches have to be examined. In this article, we propose a non-intrusive, accurate tool chain, which can reveal and quantify slowdowns in low-level software mechanisms. Based on emulation, this tool chain extracts behavioral information (time, contention) through hardware side channels, without distorting the software execution flow. This tool consists of two parts. (1) An online acquisition part that dumps hardware platform signals. (2) An offline processing part that consolidates meaningful behavioral information from the dumped data. Using our tool chain, we studied and propose optimizations to MultiProcessor System on Chip (MPSoC) support in the Linux kernel, saving about 60% of the time required for the release phase of the GNU OpenMP synchronization barrier when running on a 64-core MPSoC.

Subnanosecond Time Synchronization Using a 100Base-TX Ethernet Transceiver and an Optimized PI-Clock Servo

This work presents a real-time 100Base-TX Ethernet physical layer (PHY) transceiver chip implemented in a 180-nm technology. The PHY chip implements highly accurate hardware timestamping by using an 8-bit digital-to-phase converter (DPC) generating 256 phases of the 125 MHz system clock. Using these clock phases, spaced 31.25 ps apart from each other, phase relationships can be evaluated to timestamp ingress and egress frames with improved resolution. Connected by up to 120-m-long category five unshielded twisted-pair cables, two of these PHY chips are used to demonstrate the synchronization in a two-node scenario. A proportional-integral (PI)-clock servo is used at the slave for the synchronization. To optimize the performance, the parameters of the controller need to be chosen carefully. To do so, a simple model is used to find a suitable bandwidth of the controller as a tradeoff between the noise of the timestamping and the noise of the oscillator. All in all, a synchronization accuracy with a standard deviation of only 64 ps and a mean offset of well below 100 ps is achieved in the given scenario. To the best of our knowledge, this is the highest synchronization accuracy over copper-based Ethernet reported to date.

Error-aware Design Procedure to Implement Energy-efficient Approximate Squaring Hardware

Background:: In recent years, there has been a high demand for executing digital signal processing and machine learning applications on energy-constrained devices. Squaring is a vital arithmetic operation used in such applications. Hence, improving the energy efficiency of squaring is crucial. Objective:: In this paper, a novel approximation method based on piecewise linear segmentation of the square function is proposed. Methods: Two-segment, four-segment and eight-segment accurate and energy-efficient 32-bit approximate designs for squaring were implemented using this method. The proposed 2-segment approximate squaring hardware showed 12.5% maximum relative error and delivered up to 55.6% energy saving when compared with state-of-the-art approximate multipliers used for squaring. Results: The proposed 4-segment hardware achieved a maximum relative error of 3.13% with up to 46.5% energy saving. Conclusion:: The proposed 8-segment design emerged as the most accurate squaring hardware with a maximum relative error of 0.78%. The comparison also revealed that the 8-segment design is the most efficient design in terms of error-area-delay-power product.

Designing Electronic Systems Using SystemC and SystemC–AMS

Current trends in the design of electronic systems is the use of embedded systems based on systems on a chip (System-on-Chip (SoC)) or (VLSI SoC). The paper discusses the design features of electronic systems on a chip using the SystemC design and verification language. For the joint design and simulation of digital systems hardware and software, seven modeling levels are presented and discussed: executable specification, disabled functional model, temporary functional model, transaction-level model, behavioral hardware model, accurate hardware model, register transfer model. The SystemC design methodology with functional verification is presented, which reduces development time.The architecture of the SystemC language and its main components are shown. The expansion of SystemC–AMS for analog and mixed analog-digital signals and its use cases in the design of electronic systems are considered. Computing models are discussed: temporary data stream (TDF), linear signal stream (LSF) and electric linear networks (ELN). The architecture of the SystemC–AMS language standard is shown and examples of its application are given. It is shown that the design languages SystemC and SystemC–AMS are widely used by leading developers of computer-aided design systems for electronic devices.

He-ion Beam Imaging for Accurate Hardware Trojan Detection

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Joint Torque Estimation Using sEMG and Deep Neural Network

With the aid of various physical and biological sensors, research is actively being conducted to understand the intention of wearer’s motions through parameters such as joint torque. sEMG signals can be measured faster than physical sensors, which are often used in the field of behavioral intent identification studies. However, electrodes must be placed in the correct positions, and due to the high volume of noise, professional knowledge and accurate hardware design are required. In this paper, a system is constructed to improve the sEMG signal measurement environment by producing small multichannel sEMG modules. In addition, deep neural network supervised learning algorithms are implemented to estimate the torque using only the sEMG signal. Based on this, we analyze the organization of algorithms, the processing of the sEMG data, and how the number of channels affects learning. The optimal deep natural network model selected by the analysis is implanted to embedded after learning. The implanted model performs a portable real-time torque optimization (PRTE) according to the sEMG signal entered. In this paper, we study the deep natural network algorithm for estimating sEMG hardware and torque, and how it is implanted into a portable embedded system for use in estimating real-time motion intent. The proposed deep natural network algorithm and the usefulness of the PRTE system are verified through experiments.

EnsembleHMD: Accurate Hardware Malware Detectors with Specialized Ensemble Classifiers

Hardware-based malware detectors (HMDs) are a promising new approach to defend against malware. HMDs collect low-level architectural features and use them to classify malware from normal programs. With simple hardware support, HMDs can be always on, operating as a first line of defense that prioritizes the application of more expensive and more accurate software-detector. In this paper, our goal is to increase the accuracy of HMDs, to improve detection, and reduce overhead. We use specialized detectors targeted towards a specific type of malware to improve the detection of each type. Next, we use ensemble learning techniques to improve the overall accuracy by combining detectors. We explore detectors based on logistic regression (LR) and neural networks (NN). The proposed detectors reduce the false-positive rate by more than half compared to using a single detector, while increasing their sensitivity. We develop metrics to estimate detection overhead; the proposed detectors achieve more than 16.6x overhead reduction during online detection compared to an idealized software-only detector, with an 8x improvement in relative detection time. NN detectors outperform LR detectors in accuracy, overhead (by 40 percent), and time-to-detection of the hardware component (by 5x). Finally, we characterize the hardware complexity by extending an open-core and synthesizing it on an FPGA platform, showing that the overhead is minimal.

Building an accurate hardware Trojan detection technique from inaccurate simulation models and unlabelled ICs

Most of prior hardware Trojan detection approaches require golden chips for references. A classification-based golden chips-free hardware Trojan detection technique has been proposed in the authors' previous work. However, the algorithm in that work is trained by simulated ICs without considering a shift between the simulation and silicon fabrication. In this study, a co-training based hardware Trojan detection method by exploiting inaccurate simulation models and unlabeled fabricated ICs is proposed to provide reliable detection capability when facing fabricated ICs, which eliminates the need of golden chips. Two classification algorithms are trained using simulated ICs. These two algorithms can identify different patterns in the unlabelled ICs during test-time, and thus can label some of these ICs for the further training of the other algorithm. Moreover, a statistical examination is used to choose ICs labelling for the other algorithm. A statistical confidence interval based technique is also used to combine the hypotheses of the two classification algorithms. Furthermore, the partial least squares method is used to preprocess the raw data of ICs for feature selection. Both EDA experiment results and field programmable gate array (FPGA) experiment results show that the proposed technique can detect unknown Trojans with high accuracy and recall.

Memristive Fully Convolutional Network: An Accurate Hardware Image-Segmentor in Deep Learning

As well known, fully convolutional network (FCN) becomes the state of the art for semantic segmentation in deep learning. Currently, new hardware designs for deep learning have focused on improving the speed and parallelism of processing units. This motivates memristive solutions, in which the memory units (i.e., memristors) have computing capabilities. However, designing a memristive deep learning network is challenging, since memristors work very differently from the traditional CMOS hardware. This paper proposes a complete solution to implement memristive FCN (MFCN). Voltage selectors are firstly utilized to realize max-pooling layers with the detailed MFCN deconvolution hardware circuit by the massively parallel structure, which is effective since the deconvolution kernel and the input feature are similar in size. Then, deconvolution calculation is realized by converting the image into a column matrix and converting the deconvolution kernel into a sparse matrix. Meanwhile, the convolution realization in MFCN is also studied with the traditional sliding window method rather than the large matrix theory to overcome the shortcoming of low efficiency. Moreover, the conductance values of memristors are predetermined in Tensorflow with ex-situ training method. In other words, we train MFCN in software, then download the trained parameters to the simulink system by writing memristor. The effectiveness of the designed MFCN scheme is verified with improved accuracy over some existing machine learning methods. The proposed scheme is also adapt to LFW dataset with three-classification tasks. However, the MFCN training is time consuming as the computational burden is heavy with thousands of weight parameters with just six layers. In future, it is necessary to sparsify the weight parameters and layers of the MFCN network to speed up computing.

Haptic Augmentation for Teleoperation through Virtual Grasping Points.

Future challenges in teleoperation arise from a new complexity of tasks and from constraints in unstructured environments. In industrial applications as nuclear research facilities, the operator has to manipulate large objects whereas medical robotics requires extremely high precision. In the last decades, research optimized the transparency in teleoperation setups through accurate hardware, higher sampling rates, and improved sensor technologies. To further enhance the performance in telemanipulation, the idea of haptic augmentation has been briefly introduced in [Panzirsch etal., IEEE ICRA, 2015, pp. 312-317]. Haptic augmentation provides supportive haptic cues to the operator that promise to ease the task execution and increase the control accuracy. Therefore, an additional haptic interface can be added into the control loop. The present paper introduces the stability analysis of the resulting multilateral framework and equations for multi-DoF coupling and time delay control. Furthermore, a detailed analysis via experiments and a user study is presented. The control structure is designed in the network representation and based on passive modules. Through this passivity-based modular design, a high adaptability to new tasks and setups is achieved. The results of the user study indicate that the bimanual control brings large benefits especially in improving rotational precision.

Design of Digital Satellite Processors: From Communications Link Performance to Hardware Complexity

Latest developments in satellite communications encompass semitransparent transponder architectures. Such architectures have potentials: 1) to operate with enhanced frequency planning flexibility and physical layer specifications of evolving communications standards and 2) to support dynamic reconfiguration of connectivity plans. In this frame, significant on-board digital processing is involved, which calls for careful system modeling and accurate digital hardware design to achieve feasible tradeoffs between hardware efficiency and overall link-budget performance. In our recent works, we have proposed and validated a quantitative framework for performance analysis and design of digital transparent processors (DTPs): the model relies on an extended notion of noise figure that allows a radio link-budget to natively incorporate the nonideal behavior (e.g., quantization and rounding errors and linear distortions) of the various DTP segments. This paper complements the previous works by providing: 1) an explicit computation of implementation complexity of a DTP and 2) a methodology to carry out a complete design flow that moves from system requirements and brings to a detailed definition of digital hardware (HW) components in the DTP. Through numerical examples, we demonstrate that, given a requirement on the overall link budget performance in contexts of practical interest, significant differences in HW complexity are obtained for different design choices.

Real-time modeling, control and optimization of turbo-machinery auxiliary plants

In the Oil & Gas industry, the testing of auxiliary lubrication plants represents a mandatory preliminary activity before the whole turbo-machinery train (including the auxiliary lubrication plant) can be put in operation. To this end, the employment of both efficient and accurate plant models becomes very important to synthesize satisfactory control strategies for both testing and normal operation purposes. This way, many benefits (e.g. in terms of safety, times and costs of execution) can be achieved. Therefore, this article focuses on the development of innovative and efficient real-time models and control architectures to describe and regulate the auxiliary lubrication systems. All the new strategies have been validated through accurate real experimental campaign and real-time hardware. According to the Bond-Graph modeling strategy, an efficient lumped parameter model of the lube oil console has been built to properly optimize the description of such system and the efficiency of the control strategies...