Accurate Analog-to-digital Converter Research Articles

Research on Analog-to-Digital Converter (ADC) Dynamic Parameter Method Based on the Sinusoidal Test Signal

The acquisition of dynamic analog-to-digital converter (ADC) parameters is becoming increasingly relevant as electronic information develops at a rapid pace. The fundamental challenge of the spectrum test for ADC is that coherent sampling is difficult to achieve, especially because of the high accuracy of the excitation signal necessary for coherent sampling. Therefore, incoherent sampling is certainly unavoidable in the actual test. If the coherent sampling condition is not reached in the test, spectrum leaks from test data after Discrete Fourier Transform (DFT) analysis, resulting in inaccurate parameters. In this study, a new breakdown and reconstruction method was presented using the Ensemble Empirical Mode Decomposition (EEMD); Hilbert transform and parameter fitting method can accurately estimate the incoherent fundamental and harmonic waves, then reconstruct them to obtain accurate ADC dynamic parameters.

An Interpolation-Based Calibration Architecture for Pipeline ADC With Nonlinear Error

The linearity of a pipeline analog-to-digital converter (ADC) is mainly limited by capacitor mismatch and finite operational amplifier (OPAMP) gain, which cause large power and design difficulty in modern nanometer CMOS processes for high-resolution pipeline ADCs. It is a trend of developing digital calibration techniques to compensate the analog error in pipeline stages. This paper systematically introduces a novel interpolation-based digital calibration architecture to compensate both linear and nonlinear errors from pipeline stages. The new method does not require convergence. The effect of calibration error is analyzed in detail in this paper. A prototype 20-MS/s pipeline ADC is fabricated in a 0.35-μm 3.3-V CMOS process. For 12-b resolution, the digital calibration improves the ADC differential nonlinearity and integral nonlinearity from 1.47 LSB and 7.85 LSB to 0.2 LSB and 0.27 LSB. For a 590-kHz sinusoidal signal, the calibration improves the ADC signal-to-noise-distortion ratio and spurious-free dynamic range from 41.3 dB and 52.1 dB to 72.5 dB and 84.4 dB, respectively. With the new calibration technique, low-gain OPAMPs and small capacitors are used in the pipeline. The designed ADC has 0.78-pJ/step figure of merit (FOM), which is among the lowest reported FOMs for high-resolution pipeline ADC designs. The new architecture requires an accurate calibration ADC (CalADC) and two digital decoders. CalADC is implemented on-chip with 6.5% die area and 8.9% power. The decoders are synthesized to have 912 gates and consume 23.4% ADC power.

Study on Ocean Wind Vector Retrieval from ERS‐2 SAR Image

AbstractSAR (Synthetic Aperture Radar) wind retrieval is a hot research topic in current Remote Sensing field. In this paper the principle of space borne SAR ocean wind retrieval and three related retrieval algorithms are introduced firstly. Then, the flowchart of the retrieval procedures is provided. As an example, ERS‐2 SAR image covering Hong Kong region acquired on May 7, 2002 is used for wind vector retrieval. The classic SAR Wind Direction Algorithm ‐ spectral method is improved, and applied for the retrieval. The wind direction thus estimated is however with 180º ambiguity. Buoy data collected by the Hong Kong Observatory are then used to resolve the uncertainty. Finally, the GMF (Geophysical Model Function)‐CMOD4 is adopted to estimate the wind speed at the height of 10 m above sea level. Compared with the data recorded by Hong Kong Observatory, the error in the wind direction and average wind speed are very small. The results show that accurate ADC (Analog to Digital Converter) compensation and image calibration, together with improved SWDA and CMOD4 algorithms, could offer high quality wind vector.

A Deterministic Dynamic Element Matching Approach for Testing High-Resolution ADCs With Low-Accuracy Excitations

Dynamic element matching (DEM) is capable of providing good average linearity performance in matching critical circuits in the presence of major component mismatch, but the approach has received minimal industrial adoption outside of /spl Sigma/-/spl Delta/ structures because of challenges associated with implementation of a required randomizer and because of the time-local nonstationarity. This paper presents a DEM approach to analog-to-digital converter (ADC) testing in which low-precision DEM digital-to-analog converters (DACs) are used to generate stimulus signals for ADCs under test. It is shown that in a testing environment, this approach provides very high precision test results, and time-local nonstationarity is of no concern. In addition to traditional random DEM techniques, a deterministic DEM (DDEM) strategy that eliminates the need for a randomizer is introduced. The performance of the DDEM method is established mathematically and validated with detailed simulation results. Furthermore, the DDEM method requires far fewer samples to achieve the same level of average linearity than the random DEM approach. It is demonstrated that both the random DEM and DDEM methods can be used to accurately test ADCs with linearity that far exceeds that of the DAC used as a signal generator. This technique of using imprecise excitations and DEM to test much more accurate ADCs offers potential for use in both production test and built-in self-test environments where high linearity test sources are difficult to implement.

Least Mean Square Adaptive Digital Background Calibration of Pipelined Analog-to-Digital Converters

We present an adaptive digital technique to calibrate pipelined analog-to-digital converters (ADCs). Rather than achieving linearity by adjustment of analog component values, the new approach infers component errors from conversion results and applies digital postprocessing to correct those results. The scheme proposed here draws close analogy to the channel equalization problem commonly encountered in digital communications. We show that, with the help of a slow but accurate ADC, the proposed code-domain adaptive finite-impulse-response filter is sufficient to remove the effect of component errors including capacitor mismatch, finite op-amp gain, op-amp offset, and sampling-switch-induced offset, provided they are not signal-dependent. The algorithm is all digital, fully adaptive, data-driven, and operates in the background. Strong tradeoffs between accuracy and speed of pipelined ADCs are greatly relaxed in this approach with the aid of digital correction techniques. Analog precision problems are translated into the complexity of digital signal-processing circuits, allowing this approach to benefit from CMOS device scaling in contrast to most conventional correction techniques.