Accuracy Of Small-signal Model Research Articles

Current Tracking Delay Effect Minimization for Digital Peak Current Mode Control of DC–DC Boost Converter

Digital peak current mode (DPCM) control is widely used for dc–dc converters operating in continuous current mode. However, current tracking delay (CTD) in the system is normally neglected in the modeling stage, which leads to poor compensator design and degraded performance. This paper investigates CTD effect in boost converter with different DPCM controls. Based on dynamic relationship between the reference current and actual inductor current, the CTD transfer functions are derived, which improves the accuracy of small signal model. Since CTD degrades the phase margin of the system, equivalent migration of right half plane zero is proposed to model CTD effect. This method is very simple and straightforward, which facilitates the compensator design. Furthermore, two novel DPCM control strategies with minimized CTD are proposed, and they are based on duty cycle restriction and duty cycle extension, respectively. Both controls greatly reduce the CTD effect and improve the response speed. Besides, the duty cycle extension benefits from an extended pulsewidth modulation (ExPWM). This optimizes the calculation algorithm and speed, while improving the time margin for digital calculations. Combined with the proposed models and controls, the CTD effect is greatly reduced. The effectiveness is verified through detailed simulations and experiments.

Bias-dependent Access Resistances Extraction in 0.15 µm GaAs pHEMTs

Devices’ performance analysis and successful circuit design strongly depend on accurate large signal models. This, in turn, requires accurate small signal models. However, the reliable parasitic parameter extraction of GaAs pHEMT greatly influences the accuracy of small signal models, which also greatly influences the extraction of intrinsic elements. The access parasitic source and drain resistances, Rs and Rd, are associated with gate bias due to the two-dimensional charge control. In this work, we directly extract Rs and Rd from S-parameter measurements of the device under test (DUT) under strong inversion operating biases. The proposed method has been validated by simulation and on-wafer measurements. It shows better accuracy than existing arts in a frequency range of 0.5–40 GHz (0.5 GHz step). Furthermore, a 10-15 GHz GaAs pHEMT power amplifier (PA) is employed to further validate the developed method. The test results also validate the developed method.

A New Method to Extract Gate Bias-Dependent Parasitic Resistances in GaAs pHEMTs

Accurate large signal GaAs pHEMT models are essential for devices’ performance analysis and microwave circuit design. This, in turn, mandates precise small signal models. However, the accuracy of small signal models strongly depends on reliable parasitic parameter extraction of GaAs pHEMT, which also greatly influences the extraction of intrinsic elements. Specifically, the parasitic source and drain resistances, R s and R d , are gate bias-dependent, due to the two-dimensional charge variations. In this paper, we propose a new method to extract R s and R d directly from S-parameter measurements of the device under test (DUT), which save excessive measurements and complicated parameter extraction. We have validated the proposed method in both simulation and on-wafer measurement, which achieves better accuracy than the existing state-of-the-art in a frequency range of 0.5–40 GHz. Furthermore, we develop a GaAs pHEMT power amplifier (PA) to further validate the developed model. The measurement results of the PA at 9–15 GHz agree with the simulation results using the proposed model.