Accumulation Of Phase Error Research Articles

Pseudo multishot echo-planar imaging for geometric distortion improvement.

Conventional echo-planar imaging (EPI) uses a radiofrequency pulse for excitation and a prolonged echo train to sample k space, while off-resonance and T2 * decay effects caused by magnetic susceptibility variation accumulate within each echo, leading to geometric distortion. Multishot EPI methods, which divide k space into segments, can shorten the effective echo spacing and reduce the distortion on EPI images. But multiple shots cost longer scan time and render susceptibility to motion. In this study, we propose a new "multishot" EPI method termed pseudo multishot EPI (pmsEPI), in which phase-encoding lines are segmented as in multishot EPI but are collected within a single shot. With the magnetization divided into different pathways via interleaved excitation instead of refocusing in a single long echo train, the total phase error accumulation is reduced in each segmented acquisition, thereby improving distortion of the resultant EPI image. The performance of the pmsEPI method is demonstrated by phantom and in vivo brain experiments on a 3-T scanner. The experimental results show that the distortion displacements of pmsEPI acquisition compared with conventional EPI decrease by 50% with two pseudo shots and 66% with three pseudo shots, validating the ability of the method to obtain images with reduced distortion in a single shot, although magnetization splitting may induce more than 40% SNR loss and minor artifacts. Specifically, the ability of pmsEPI in diffusion-weighted imaging with different trajectory options is highlighted, and the flexibility is demonstrated in a single-shot blip up and down acquisition.

Phase measuring profilometry based on binary grating projection for fringe order self-extraction

A phase measuring profilometry (PMP) based on binary grating projection for fringe order self-extraction is proposed. In traditional PMP based on sinusoidal grating projection, the phase is wrapped between (−π, π] due to the arctangent operation. And wrapped phase needs to be unwrapped using relative phase unwrapping algorithms such as diamond-type phase unwrapping algorithm in which the accumulation of phase errors is easy to occur or even lead to wrong phase unwrapping; or with the assistance of some additional structured light patterns such as Gray code, the fringe order may be determined to achieve phase unwrapping without the phase error accumulation. In the proposed method, three-dimensional measurement is achieved by just projecting a set of phase-shifted binary gratings, which can not only avoid the gamma non-linearity influence of the projector, but also increase the refresh frequency of the projector by more than ten times. At the same time, by using the image characteristics of the binary grating itself, the fringe order can be extracted without increasing any additional structured light pattern. So that the phase unwrapping can be achieved by combining the phase of extracted fringe order with the wrapped phase without the phase error accumulation. The experimental results verify the feasibility and effectiveness of the proposed method, and the solution result is in good agreement with the solution result of the diamond algorithm without cumulative errors.

Design and Implementation of a Farrow-Interpolator-Based Digital Front-End in LTE Receivers for Carrier Aggregation

A digital front-end decimation chain based on both Farrow interpolator for fractional sample-rate conversion and a digital mixer is proposed in order to comply with the long-term evolution standards in radio receivers with ten frequency modes. Design requirement specifications with adjacent channel selectivity, inband blockers, and narrowband blockers are all satisfied so that the proposed digital front-end is 3GPP-compliant. Furthermore, the proposed digital front-end addresses carrier aggregation in the standards via appropriate frequency translations. The digital front-end has a cascaded integrator comb filter prior to Farrow interpolator and also has a per-carrier carrier aggregation filter and channel selection filter following the digital mixer. A Farrow interpolator with an integrate-and-dump circuitry controlled by a condition signal is proposed and also a digital mixer with periodic reset to prevent phase error accumulation is proposed. From the standpoint of design methodology, three models are all developed for the overall digital front-end, namely, functional models, cycle-accurate models, and bit-accurate models. Performance is verified by means of the cycle-accurate model and subsequently, by means of a special C++ class, the bitwidths are minimized in a methodic manner for area minimization. For system-level performance verification, the orthogonal frequency division multiplexing receiver is also modeled. The critical path delay of each building block is analyzed and the spectral-domain view is obtained for each building block of the digital front-end circuitry. The proposed digital front-end circuitry is simulated, designed, and both synthesized in a 180 nm CMOS application-specific integrated circuit technology and implemented in the Xilinx XC6VLX550T field-programmable gate array (Xilinx, San Jose, CA, USA).

Study on Multi-GNSS Precise Point Positioning Performance with Adverse Effects of Satellite Signals on Android Smartphone.

The emergence of dual frequency global navigation satellite system (GNSS) chip actively promotes the progress of precise point positioning (PPP) technology in Android smartphones. However, some characteristics of GNSS signals on current smartphones still adversely affect the positioning accuracy of multi-GNSS PPP. In order to reduce the adverse effects on positioning, this paper takes Huawei Mate30 as the experimental object and presents the analysis of multi-GNSS observations from the aspects of carrier-to-noise ratio, cycle slip, gradual accumulation of phase error, and pseudorange residual. Accordingly, we establish a multi-GNSS PPP mathematical model that is more suitable for GNSS observations from a smartphone. The stochastic model is composed of GNSS step function variances depending on carrier-to-noise ratio, and the robust Kalman filter is applied to parameter estimation. The multi-GNSS experimental results show that the proposed PPP method can significantly reduce the effect of poor satellite signal quality on positioning accuracy. Compared with the conventional PPP model, the root mean square (RMS) of GPS/BeiDou (BDS)/GLONASS static PPP horizontal and vertical errors in the initial 10 min decreased by 23.71% and 62.06%, respectively, and the horizontal positioning accuracy reached 10 cm within 100 min. Meanwhile, the kinematic PPP maximum three-dimensional positioning error of GPS/BDS/GLONASS decreased from 16.543 to 10.317 m.

A Low-Jitter Fast-Locked All-Digital Phase-Locked Loop With Phase–Frequency-Error Compensation

The previous fast-locked all-digital phase-locked loop (ADPLL) usually suffers from large timing jitter due to the steep frequency transfer curve of its digitally controlled oscillator (DCO). This paper presents an ADPLL that possesses a coarse frequency selection function. All DCO frequency transfer curves of the ADPLL have gentle slopes. The ADPLL selects one transfer curve before acquisition. To fulfill the fast-acquisition requirement, the proposed ADPLL employs the phase–frequency-error compensation technique. In the acquisition mode, the phase-error compensator resolves the problem of phase-error accumulation. Meanwhile, the frequency-error compensator predicts a proper control code by calculating the cycle time difference between the reference clock and the derived signal fed back from the DCO. Therefore, the proposed ADPLL can compensate for the phase and the frequency errors simultaneously. The experimental results show that the proposed ADPLL possesses a fine-tuning acquisition within 5 reference clock cycles. After acquisition, the code updates in a fractional manner in the tracking mode to enhance the tracking jitter performance. The ADPLL output frequency ranges from 860 MHz to 1 GHz. The measured rms jitter is 1.31 ps at 1-GHz frequency.

Use of the effect of phase error accumulation in ring oscillators to estimate time parameters of digital elements of integrated circuits

A novel approach to determining time parameters of digital library IC elements with the use of built-in digital measuring modules arranged on the test chip is offered. It is shown that using the phase error accumulation methodology in ring oscillators with the investigated elements makes it possible to measure the averaged rising and falling delays of signals with picosecond accuracy. Use of digital elements will allow us to provide a technology-independent solution when one manufacturing method used at a plant changes to another one without modifying the circuits of the measurement module and the measuring technique.

Can Analog PLLs Hold Lock? A Paradox Explored [Open Column

This article has extended the methods of earlier workers to devise formulas that predict the variance of phase-error accumulation in type-1 PLLs in response to h <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /f <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> phase noise. The formulas are in terms of engineering specifications of the PLLs and of measurable specifications of phase noise spectra. Numerous approximations have been made so that the formulas cannot be expected to be highly accurate. More significantly, the analysis does not prove that the phase error accumulation actually occurs; the theory that implicitly underlies the formulas may not be valid under the conditions postulated. An experiment to test the predictions would be a worthy project.