Memory Access Speed Research Articles

Competitive cost-effective memory access predictor through short-term online SVM and dynamic vocabularies

In recent years, there has been a significant increase in the processing of massive amounts of data, driven by the growing demands of mobile systems, parallel and distributed architectures, and real-time systems. This applies to various types of platforms, both specific and general-purpose. Despite numerous advancements in Computer Systems, a critical challenge remains: the efficiency and speed of memory access. This bottleneck is being addressed through cache prefetching, that is, by predicting the next memory address to be accessed and then by having always prefetched in the cache system those data to be used shortly by the processor. This paper explores established intelligent techniques for address prediction, examining their limitations and analyzing the memory access patterns of popular software applications. Building on the successes of previous intelligent predictors based on Machine and Deep Learning models, we introduce a new predictor, SVM4AP (Support Vector Machine For Address Prediction), designed to overcome the identified drawbacks of its predecessors. The architecture of SVM4AP improves the trade-off between performance and cost, compared to those previous proposals in the literature, achieving high accuracy through short-term learning. Comparisons are made with two prominent predictors from the literature: the classical DFCM (Differential Finite Context Method) and the contemporary Deep Learning-based DCLSTM (Doubly Compressed Long-Short Term Memory). The results demonstrate that SVM4AP achieves superior cost-effectiveness across various configurations. Simulations reveal that SVM4AP configurations dominate both DFCM and DCLSTM counterparts, forming the majority of the first Paretto front. Particularly noteworthy is the significant advantage of our proposal for small-size predictors. Furthermore, we release an open-source tool enabling the scientific community to reproduce the results presented in this paper using a set of benchmark traces.

Post-hypnotic suggestion improves confidence and speed of memory access with long-lasting effects

In our study, we use the post-hypnotic suggestion of easy remembering to improve memory with long-lasting effects. We tested 24 highly suggestible participants in an online study. Participants learned word lists and recalled them later in a recognition memory task. At the beginning of the study, participants were hypnotized and the post-hypnotic suggestion to remember easily was associated with a cue that participants used during the recognition memory task. In a control condition, the same participants used a neutral cue. One week later, participants repeated both conditions with new word lists.Participants were significantly faster and more confident in their recognition ratings in the easy-remembering condition compared to the control condition, and this effect persisted over one week. Crucially, the increased speed and confidence in the easy-remembering condition did not affect memory accuracy. That makes our hypnosis intervention promising for patients experiencing subjective memory impairments. APA PsycINFO codes2343 (Learning and Memory), 2380 (Consciousness States), 3351 (Clinical Hypnosis)

Towards a metrics suite for evaluating cache side-channel vulnerability: Case studies on an open-source RISC-V processor

Caches are key microarchitectural components of modern processors to improve memory access speed. However, attackers can readily implement timing side-channel attacks by exploiting the inherent time difference between cache hits and misses, which brings serious security threats to computer systems. In recent years, cache attacks have achieved fruitful consequences regarding attack techniques, targets, and platforms. At the same time, in order to measure the cache vulnerability, researchers have been looking at verifying the security policies and have proposed a variety of evaluation metrics. However, there are certain limitations in the current metrics, such as harsh assumptions, the distinguishing ability cannot be maintained all the time, the false positive and false negative noises can not be explicitly quantified, other tools are needed, and the verification environment is difficult to reproduce. To face these issues, we proposed a set of evaluation metrics, which includes the highest score (HS), minimum rounds to disclosure (MRD), and key score scissors differential (KSSD); we give the formal expressions in practice and theoretical, respectively. In order to facilitate the accurate reproduction of the experimental environment and results, we build a dual-core RISC-V bare-metal system based on the open-source framework Chipyard. On this basis, we conduct comprehensive evaluations to exploit vulnerabilities within the RISC-V cache architecture to verify the validity of the metrics suite. Furthermore, we compared the metrics with the commonly used success rate (SR) and guessing entropy (GE). The comparison results show that our proposed metrics suite can accurately depict the effects of attacks. Moreover, KSSD can maintain discrimination and converge quickly; MRD has more practical guidance; HS can specifically describe false negative noises. Finally, we perform a theoretical evaluation of AES algorithms with different T-table implementations using the proposed metrics, analyze the system's false positive and false negative noises, and suggest how the number of cache evictions can be determined under the random replacement policy.

Optimized Implementation of Argon2 Utilizing the Graphics Processing Unit

In modern information technology systems, secure storage and transmission of personal and sensitive data are recognized as important tasks. These requirements are achieved through secure and robust encryption methods. Argon2 is an advanced cryptographic algorithm that emerged as the winner in the Password Hashing Competition (PHC), offering a concrete and secure measure. Argon2 also provides a secure mechanism against side-channel attacks and cracking attacks using parallel processing (e.g., GPU). In this paper, we analyze the existing GPU-based implementation of the Argon2 algorithm and further optimize the implementation by improving the performance of the hashing function during the computation process. The proposed method focuses on enhancing performance by distributing tasks between CPU and GPU units, reducing the data transfer cost for efficient GPU-based parallel processing. By shifting several stages from the CPU to the GPU, the data transfer cost is significantly reduced, resulting in faster processing times, particularly when handling a larger number of passwords and higher levels of parallelism. Additionally, we optimize the utilization of the GPU’s shared memory, which enhances memory access speed, especially in the computation of the hash value generation process. Furthermore, we leverage the parallel processing capabilities of the GPU to perform efficient brute-force attacks. By computing the H function on the GPU, the proposed implementation can generate initial blocks for multiple inputs in a single operation, making brute-force attacks in an efficient way. The proposed implementation outperforms existing methods, especially when processing a larger number of passwords and operating at higher levels of parallelism.

Vina-FPGA: A Hardware-Accelerated Molecular Docking Tool With Fixed-Point Quantization and Low-Level Parallelism

Molecular docking (MD) is one of the core steps in the expensive and time-consuming process of drug design, which is basically an optimization problem based on scoring functions. AutoDock series MD software is widely accepted by academia and industry, among which AutoDock Vina (Vina) is the latest and most popular version due to its accuracy and relatively high speed. However, contrast to its prior version, i.e., AutoDock4, hardware acceleration approaches of Vina are rarely reported. In this article, we propose Vina-field-programmable gate array (FPGA), a hardware-accelerated Vina implementation with FPGA that exploits the low-level parallelism. First, the fixed-point quantization is analyzed and realized to accelerate the MD algorithm with a better energy efficiency in hardware. To boost the performance of the module-level computation, multiple in- module hardware pipelines have been designed and implemented. Besides, a strategy for fast accessing to block RAM (BRAM) is implemented by utilizing the layout of data, which brings four times memory access speed to the intermolecular and intramolecular energy computing modules. Under the same 140 ligand–receptor benchmarks, Vina-FPGA performs up to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6.9\times $ </tex-math></inline-formula> (average <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.7\times$ </tex-math></inline-formula> ) faster than a state-of-the-art CPU does while consuming only 2.5% energy with similar docking accuracies. Compared to the GPU-accelerated implementation or Vina-GPU, the average energy consumption of Vina-FPGA is merely 45%.

Art Installation Design and Algorithm Research Oriented to Heterogeneous Computing Architecture and Particle Swarm Algorithm

Traditional high-performance computers generally use commercial general-purpose processors. When constructing large-scale parallel computing systems, they will face many challenges in system efficiency, power consumption, system maintenance, and cost. Heterogeneous architectures have begun to become the key to constructing supercomputer systems. In order to improve the optimization efficiency of the particle swarm algorithm, based on the simplified particle swarm algorithm, an improved strategy for fusion of population information is proposed. Only using the optimal position of the individual particle and the optimal position of the population to update the particle position makes the algorithm description simpler, construct a random term that depends on the population information to increase the diversity of the population, and design an adaptive control function equation to balance the algorithm's global detection and local detection. This article aims to study the design and algorithm of art installations for heterogeneous computing architecture and particle swarm algorithm. Aiming at the two heterogeneous system components of GPU and FPGA in heterogeneous computing systems to solve the dual heterogeneous problem between various computing components and applications, a task flow model for heterogeneous computing systems is proposed, which adopts heterogeneous systems. The structure focuses on the deterministic and nondeterministic calculation methods of particle swarm algorithm and carries out parallel research algorithms of particle transport data to analyze the design of art installations. The experimental results show that by making full use of the GPU hardware storage structure to improve memory access speed and reduce cache failure, the combination of particle swarm algorithm and heterogeneous computing system enables the calculation of the carrier components to obtain 3 times the acceleration effect; through the energy analysis model, Heterogeneous computing system components can obtain at least 1.5 times performance improvement.

Score Based Garbage Collection Algorithm for Flash Based Storage System

A solid-state drive’s garbage collection technique considerably influences the drive’s writing performance and life duration. The garbage collection technique chooses the block to be erased so that the block can be reused. Several techniques, such as hot data identification, enhance the efficiency of garbage collection and impact flash memory access speed and lifespan. This paper proposes a garbage collection algorithm, SGC (Score-based Garbage Collection) which tries to identify data on the basis of threshold into hot and cold blocks then the process is followed by choosing victim block with the help of score for garbage collection. The SGC approach minimises SSD wear frequency and garbage collection overhead, extending SSD life and data reliability. A novel hot and cold identification system helps to reduces program/erasure cycles while increasing identification accuracy, basedon threshold data are clustered into hot and cold. The experimental findings illustrate that the SGC outperforms the existing approach under various benchmarks by reducing the frequency of block wear leveling. The simulation result shows how SGC performs well and lowers the costs, such as the number of copy and erase operation done, wear on the block, and energy consumption.Improvement percentage for wear leveling is calculated for input traces exchange, financial 1 and financial 2. For exchange trace our policy outperforms CB,CAT,GR and CATA by 19.04%,15.0%,37.03% and 10.5% respectively.

Fast multi-phase gain matrix computation for real time distribution system state estimation

Efficient distribution system state estimation (DSSE) is becoming increasingly important in modern grids. Building the gain matrix is carried out at every iteration of the weighted least squares (WLS) DSSE algorithm that employs the normal equations approach, and the computation of this matrix occupies a substantial portion of the total execution time. This paper presents a two-phase algorithm for the efficient gain matrix calculation suitable for modern CPU architectures. The preparation phase creates the necessary structures for effective data streaming and code execution. The gain matrix is calculated in the second phase using the prepared data and single instruction multiple data (SIMD) intrinsics. The Jacobian measurement matrix is organized as a sparse matrix of small dense blocks with double-precision complex values. The implementation exploits memory-aligned data blocks that require fewer CPU instructions and provide higher memory access speeds, in addition to modern C++ features for utilizing the instruction pipelining technique fully. Numerical results are reported on sizeable distribution networks having up to 3124 multi-phase nodes and 9537 three-phase nodes. They show that the proposed approach for computing the gain matrix is up to three times faster than the sparse matrix–matrix multiplication function in the SuiteSparse package, which makes the procedure useful for the development of real-time DSSE software.

Application-Oriented Data Migration to Accelerate In-Memory Database on Hybrid Memory.

With the advantage of faster data access than traditional disks, in-memory database systems, such as Redis and Memcached, have been widely applied in data centers and embedded systems. The performance of in-memory database greatly depends on the access speed of memory. With the requirement of high bandwidth and low energy, die-stacked memory (e.g., High Bandwidth Memory (HBM)) has been developed to extend the channel number and width. However, the capacity of die-stacked memory is limited due to the interposer challenge. Thus, hybrid memory system with traditional Dynamic Random Access Memory (DRAM) and die-stacked memory emerges. Existing works have proposed to place and manage data on hybrid memory architecture in the view of hardware. This paper considers to manage in-memory database data in hybrid memory in the view of application. We first perform a preliminary study on the hotness distribution of client requests on Redis. From the results, we observe that most requests happen on a small portion of data objects in in-memory database. Then, we propose the Application-oriented Data Migration called ADM to accelerate in-memory database on hybrid memory. We design a hotness management method and two migration policies to migrate data into or out of HBM. We take Redis under comprehensive benchmarks as a case study for the proposed method. Through the experimental results, it is verified that our proposed method can effectively gain performance improvement and reduce energy consumption compared with existing Redis database.

CuSCNN: A Secure and Batch-Processing Framework for Privacy-Preserving Convolutional Neural Network Prediction on GPU.

The emerging topic of privacy-preserving deep learning as a service has attracted increasing attention in recent years, which focuses on building an efficient and practical neural network prediction framework to secure client and model-holder data privately on the cloud. In such a task, the time cost of performing the secure linear layers is expensive, where matrix multiplication is the atomic operation. Most existing mix-based solutions heavily emphasized employing BGV-based homomorphic encryption schemes to secure the linear layer on the CPU platform. However, they suffer an efficiency and energy loss when dealing with a larger-scale dataset, due to the complicated encoded methods and intractable ciphertext operations. To address it, we propose cuSCNN, a secure and efficient framework to perform the privacy prediction task of a convolutional neural network (CNN), which can flexibly perform on the GPU platform. Its main idea is 2-fold: (1) To avoid the trivia and complicated homomorphic matrix computations brought by BGV-based solutions, it adopts GSW-based homomorphic matrix encryption to efficiently enable the linear layers of CNN, which is a naive method to secure matrix computation operations. (2) To improve the computation efficiency on GPU, a hybrid optimization approach based on CUDA (Compute Unified Device Architecture) has been proposed to improve the parallelism level and memory access speed when performing the matrix multiplication on GPU. Extensive experiments are conducted on industrial datasets and have shown the superior performance of the proposed cuSCNN framework in terms of runtime and power consumption compared to the other frameworks.

A Delay-Based Machine Learning Model for DMA Attack Mitigation

Direct Memory Access (DMA) is a state-of-the-art technique to optimize the speed of memory access and to efficiently use processing power during data transfers between the main system and a peripheral device. However, this advanced feature opens security vulnerabilities of access compromise and to manipulate the main memory of the victim host machine. The paper outlines a lightweight process that creates resilience against DMA attacks minimal modification to the configuration of the DMA protocol. The proposed scheme performs device identification of the trusted PCIe devices that have DMA capabilities and constructs a database of profiling time to authenticate the trusted devices before they can access the system. The results show that the proposed scheme generates a unique identifier for trusted devices and authenticates the devices. Furthermore, a machine learning–based real-time authentication scheme is proposed that enables runtime authentication and share the results of the time required for training and respective accuracy.

Comparative analysis of matching pursuit algorithms for Kirchhoff migration on compressed data

Currently, the amount of recorded data in a seismic survey is in the order of hundreds of Terabytes. The processing of such amount of data implies significant computational challenges. One of them is the I/O bottleneck between the main memory and the node memory. This bottleneck results from the fact that the disk memory access speed is thousands-fold slower than the processing speed of the co-processors (eg. GPUs). We propose a special Kirchhoff migration that develops the migration process over compressed data. The seismic data is compressed by using three well-known Matching Pursuit algorithms. Our approach seeks to reduce the number of memory accesses to the disk required by the Kirchhoff operator and to add more mathematical operations to the traditional Kirchhoff migration. Thus, we change slow operations (memory access) for fast operations (math operations). Experimental results show that the proposed method preserves, to a large extent, the seismic attributes of the image for a compression ratio up to 20:1.

Automatic coarse-to-fine joint detection and segmentation of underwater non-structural live crabs for precise feeding

Effective biomass detection methods utilizing computer vision techniques should be capable of handling large differences in object posture and various degrees of mutual overlap/occlusion in object scenes. We propose an automatic coarse-to-fine joint detection and instance segmentation network (JDSNet) that can perform real-time detection and instance segmentation on underwater non-structural live crabs in real-time. The method was adapted to non-structural objects and mobile devices by applying the anchor-free mechanism and center-ness strategy of the fully convolutional one-stage prediction head and the improved energy-efficient backbone IVoVNet-19-DW with identity mapping and channel attention. This approach avoided the complicated computations related to the anchor-based mechanism and effectively generated the features of various receiving domains, jointly improving the memory access speed and accuracy of predicting the bounding boxes of different instances. A novel spatial attention-guided mask branch was then added to focus on irregular occluded object pixels and conduct precise pixel-level mask segmentation within the predicted coarse instance-aware rectangular-bounding boxes. The experimental analysis using the proposed method resulted in a quality of detection F1 and segmentation Dic of 97.7% and 94.6%, respectively. The fastest detection speed of a single image was 48.07/13.32 fps (~10 times faster than the existing network Mask RCNN) on a commonly configured GPU/CPU, requiring only 7.04 MB of storage (~25 times smaller than Mask RCNN). It indicates that JDSNet can segment various non-structural live crabs and perform biomass statistics robustly and efficiently, exhibiting significance for precision feeding applications in automatic feeding boats.

Effects of anodal transcranial direct current stimulation on cognitive dysfunction in patients with progressive supranuclear palsy.

Progressive supranuclear palsy (PSP) is a tauopathy characterized by motor, neurobehavioral and disabling brainstem deficits. No disease-modifying therapeutic options exist. The therapeutic potential of transcranial direct current stimulation (tDCS) has been highlighted in studies on patients with other neurodegenerative diseases. Therefore, by drawing upon the limited tDCS literature on PSP, we conducted a pilot study in order to evaluate the effect of tDCS over motor and premotor cortex in patients with PSP, with a particular emphasis on cognitive dysfunction. Eight patients affected by PSP were included (4 males and 4 females with mean age 67.4±7.4 years, range: 55-80 years and mean disease duration: 4.6±3.3 years, range: 1-11 years). The mean Unified Parkinson's Disease Rating Scale Part III (UPDRS III) was 49±16.1 and the mean Hoehn & Yahr (H&Y) scale was 3.9±1 at baseline. All pharmacological treatments (L-dopa, pramipexole, rotigotine, rasagiline, amantadine) were maintained stable during the study. We aimed at evaluating along with the motor outcome (as it is reflected on a disease-specific rating scale), the post-tDCS cognitive status after the completion of the intervention. The clinical evaluation involved the PSP-Rating Scale, the UPDRS III and the Timed Up and Go test. Neuropsychological assessment focused on auditory-verbal memory and learning, episodic memory, visuo-motor coordination and speed of information processing, executive functions and verbal fluency (phonemic and semantic). Anodal tDCS was applied over primary motor and pre-motor cortices in 10 daily sessions. During the tDCS stimulation a constant current of 2 mA was delivered for 30 minutes. Clinical evaluations were performed at baseline, day 11, day 30 and at day 90. The PSP-Rating score (total and sections I & III) improved significantly on day 11 compared to baseline and similarly on day 30. A positive effect was also seen on action tremor. In addition to the global mental status improvement, patients showed increases in neuropsychological performance in the domains of visuo-motor co-ordination and processing speed, auditory-verbal learning, episodic memory,phonological and semantic fluency (access and retrieval from lexical memory, selective inhibition and lexical access speed). Our results suggest that tDCS has a beneficial effect on Progressive Supranuclear Palsy patients' bulbar and motor symptoms, cognitive dysfunction, as well as daily activities, which lasts beyond the duration of the treatment.

Non-volatile memory driver to drastically reduce input-output response time and maintain Linux device-mapper framework

Automated tiered storage with fast memory and slow flash storage (ATSMF) is a hybrid storage system located between non-volatile memories (NVMs) and solid state drives (SSDs). ATSMF reduces the average response time for input-output (IO) accesses by migrating concentrated IO-access areas from an SSD to an NVM. However, the current ATSMF implementation cannot sufficiently reduce the average response time because of the bottleneck caused by the Linux brd driver, which is used for the NVM access The response time of the brd driver is more than ten times longer than memory-access speed. To sufficiently reduce the average response time, we developed a block-level driver for an NVM called a two-mode (2M) memory driver. This driver has a .map-access mode and direct-access mode to reduce the response time while maintaining compatibility with the Linux device-mapper framework. The direct-access mode has a drastically lower response time than the Linux brd driver because the ATSMF driver can directly execute the IO-access function of the 2M memory Experimental results indicate that ATSMF using the 2M memory driver reduced the IO access response time to less than that of ATSMF using the Linux brd driver in most cases.

HydraFS: an efficient NUMA-aware in-memory file system

Emerging persistent file systems are designed to achieve high-performance data processing by effectively exploiting the advanced features of Non-volatile Memory (NVM). Non-uniform memory access (NUMA) architectures are universally used in high-performance computing and data centers due to its scalability. However, existing NVM-based in-memory file systems are all designed for uniformed memory access systems. Their performance is not satisfactory on NUMA machine as they do not consider the architecture of multiple nodes and the asymmetric memory access speed. In this paper, we design an efficient NUMA-aware in-memory file system which distributes file data on all nodes to effectively balance the loads of file requests. Three approaches for improving the performance of the file system on NUMA machine are proposed, including Node-oriented File Creation algorithm to dispatch files over multiple nodes, File-oriented Thread Binding algorithm to bind threads to the gainful nodes and a buffer assignment technique to allocate the user buffer from the proper node. Further, based on the new design, we implement a functional NUMA-aware in-memory file system, HydraFS, in Linux kernel. Extensive experiments show that HydraFS significantly outperforms existing representative in-memory file systems on NUMA machine. The average performance of HydraFS is 76.6%, 91.9%, 26.7% higher than EXT4-DAX, PMFS, and SIMFS, respectively.

A Novel STT-RAM-Based Hybrid Cache for Intermittently Powered Processors in IoT Devices

Emerging nonmemory technologies have been widely employed in intermittently powered the Internet of Things (IoT) devices to bridge program execution across different power cycles. Together with register contents, the cache contents will be checkpointed to nonvolatile memory upon power outages. While pure nonvolatile memory-based cache is an intuitive option, it suffers from inferior performance due to high write latency and energy overhead. We introduce a spin-transfer torque magnetic random-access memory (STT-RAM)-based hybrid cache which is specifically tailored for the intermittently powered embedded system. This cache design supports both normal memory access and checkpointing: During normal access, the large density of STT-RAM and the fast access speed of static random-access memory (SRAM) are fully taken advantage to achieve high performance and low energy consumption; during checkpointing, the most important cache blocks in SRAM are migrated to the dead or unimportant clean cache blocks in STT-RAM. This design achieves instant resumption speed without restoration of large cache state. The experimental results demonstrate a 1.3× execution progress improvement compared with a pure nonvolatile cache design.

A Monolithic 3D Hybrid Architecture for Energy-Efficient Computation

The exponentially increasing performance of chip multiprocessors (CMPs) predicted by Moore's Law is no longer due to the increasing clock rate of a single CPU core, but on account of the increase of core counts in the CMP. More transistors are integrated within the same footprint area as the technology node shrinks to deliver higher performance. However, this is accompanied by higher power dissipation that usually exceeds the coping capability of inexpensive cooling techniques. This Power Wall prevents the chip from running at full speed with all the devices powered-on. This is known as the dark silicon problem. Another major bottleneck in CMP development is the imbalance between the CPU clock rate and memory access speed. This Memory Wall keeps the CPU from fully utilizing its compute power. To address both the Power and Memory Walls, we propose a monolithic 3D hybrid architecture that consists of a multi-core CPU tier, a fine-grain dynamically reconfigurable (FDR) field-programmable gate array (FPGA) tier, and multiple resistive RAM (RRAM) tiers. The FDR tier is used as an accelerator. It uses the concept of temporal logic folding to localize on-chip communication. The RRAM tiers are connected to the CPU and FDR tiers through an efficient memory interface that takes advantage of the tremendous bandwidth available from monolithic inter-tier vias and hides the latency of large data transfers. We evaluate the architecture on two types of benchmarks: compute-intensive and memory-intensive. We show that the architecture reduces both power and energy significantly at a better performance for both types of applications. Compared to the baseline, our architecture achieves an average of 43.1× and 2.5× speedup on compute-intensive and memory-intensive benchmarks, respectively. The power and energy consumption are reduced by 5.0× and 40.5×, respectively, for compute-intensive applications, and 2.0× and 4.2×, respectively, for memory-intensive applications. This translates to 1745.3× energy-delay product (EDP) improvement for compute-intensive applications and 10.5× for memory-intensive applications.

Fast Content Updating Algorithm for an SRAM-Based TCAM on FPGA

Static random-access memory (SRAM)-based ternary content-addressable memory (TCAM), an alternative to traditional TCAM, where inclusion of SRAM improves the memory access speed, scalability, cost, and storage density compared to conventional TCAM. In order to confidently use the SRAM-based TCAMs in application, an update module (UM) is essential. The UM replaces the old TCAM contents with fresh contents. This letter proposes a fast update mechanism for an SRAM-based TCAM and implements it on Xilinx Virtex-6 field-programmable gate array. To the best of authors’ knowledge, this is the first ever proposal on content-update-module in an SRAM-based TCAM, which consumes least possible clock cycles to update a TCAM word.

Energy-Efficient Monolithic Three-Dimensional On-Chip Memory Architectures

Memory bandwidth is one of the major performance bottlenecks for chip multiprocessors (CMPs), which continue to integrate an increasing number of cores with the help of Moore's Law. The growing disparity between the CPU clock rate and offchip memory access speed is known as the Memory Wall. This problem has been actively studied in the past two decades. It is addressed by placing memory closer to the processor, such as stacking the memory directly on top of a CMP, thereby significantly reducing the interconnect latency between them. However, previous 3D-stacked memory architectures use through-silicon via (TSV)based three-dimensional (3-D) integration, which bonds multiple dies with TSVs that have diameters in the 1-5 μm range. Unlike TSV-based 3-D integration, monolithic 3-D integration builds device tiers sequentially on a single substrate. Different tiers are connected using monolithic inter-tier vias (MIVs), which have a diameter (around 50 nm) that is the same as that of a local via. Main memory typically consists of DRAM, which is volatile and thus requires periodic refresh to maintain the stored data. This increases both the energy consumption and access latency. However, various nonvolatile RAMs (NVRAMs) have emerged as possible universal memory technologies, which promise low power, fast read access, high density, and nonvolatility. In this paper, we present an efficient memory interface for monolithic 3D-stacked RAM (both DRAM and NVRAMs such as resistive RAM and nanotube RAM). It takes advantage of the tremendous bandwidth made available by MIVs to implement an on-chip memory bus in order to hide the latency of large data transfers. We propose a multientry row-based write buffer to increase the buffer hit rate and reduce the number of memory core accesses. We decouple read and write accesses using extra interconnects available through MIVs to increase memory throughput. We also present an adaptive power-down policy to maintain balance between energy efficiency and performance. Simulation results show that the proposed architecture can achieve both high performance and energy efficiency, and is thus attractive for low-power/high-performance computing.