8T Dual-port SRAM Research Articles

A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme

This paper presents a low-energy 64-Kb eight-transistor (8T) one-read/one-write dual-port image memory with a 28-nm fully depleted SOI (FD-SOI) process technology. Our proposed SRAM adopts a selective sourceline drive (SSD) scheme and a consecutive data write technique for improving active energy efficiency at low voltage. The novel SSD scheme controls sourceline voltage and eliminates leakage energy at unselected columns in read operations. We fabricated a 64-Kb 8T dual-port SRAM in the 28-nm FD-SOI process technology. The 8T SRAM cell size is $0.291 \times 1.457\,\,\mu \text{m}^{2}$ . The test chip exhibits 0.48-V operation at an access time of 135 ns. The energy minimum point is at a supply voltage of 0.56 V and an access time of 35 ns, where 265.0 fJ/cycle in write operations and 389.6 fJ/cycle in read operations are achieved. These factors are, respectively, 30% and 26% smaller than those of the 8T dual-port SRAM with the conventional scheme.

A 0.4 V 12T 2RW dual-port SRAM with suppressed common-row-access disturbance

Dual-port SRAMs with two sets of address bus and data IOs are widely employed in various applications to increase throughput. Conventional 8T dual-port SRAM suffers reliability issue at low voltages due to common-row-access disturbance. Specifically, a row is simultaneously accessed by two operations, which can flip existing data and cause incorrect read output. Previous work can address this stability issue by assisting circuitry at cost of timing. This paper presents a low voltage 12T 2RW SRAM featuring parallel access with suppressed disturbance to ameliorate the problem without performance degradation. The proposed SRAM cell suppresses the disturbance by separating read path from internal nodes and minimizing the probability of the worst case stability with area penalty of 6%. In addition, hierarchical bitlines and a virtual ground technique are employed to further lower the minimum operating voltage and power consumption. A 16kb SRAM has been fabricated in a 65nm CMOS technology and extended the operating voltage from super-threshold region to 0.4V at common-row-access scenario.