80C51 Microcontroller Research Articles

Design of Multi-Channel Wireless Alarm Based on Cortex M3 Processor

Making use of Cortex M3 processor, a multi-channel wireless alarm is proposed in this paper (patent number: 201220357699.3). The proposed multi-channel wireless alarm can be used in the place where have a large number and dense monitoring points. In order to realize the target of one receiving unit and many transmitting units, the modules of PT2262/PT2272 and STM32F103RBT6 microcontroller which had Cortex M3 core were used in this system. Compared with the traditional 80C51 microcontroller systems, this design overcome the disadvantage of the IO ports of 80C51 microcontroller which only have the high level and low level stages. This disadvantage make 80C51 microcontroller could not full use the addressing ability of PT2272 address pins which could be high resistance, high level and low level stages, So the design of this paper effectively expanding the number of alarm system monitoring.

A High Efficiency Maximum Power Point Tracker for Photovoltaic Arrays

The photovoltaic (PV) generator exhibits non- linear characteristics and its maximum power point varies with solar insolation and temperature, thus this work deals with the design and implementation of a real time maximum power point tracker(MPPT)for photovoltaic system aiming to improve energy conversion efficiency. A MPPT algorithm is developed using PV array voltage and current information's and the incremental conductance of the PV array, it's implemented by single chip 80C51 microcontroller to control the duty cycle of a boost converter with pulse width modulation (PWM). The practical and Simulation results shows the validity of the designed circuit to improve the tracking efficiencies to get the maximum power point. Key words: solar panel, Maximum Power point tracker (MPPT), microcontroller.

Low Power Techniques Applied to a 80C51 Microcontroller for High Temperature Applications

In this paper, we present a low power high temperature 80C51 microcontroller. The low power optimizations are applied at gate and architectural levels, by using extensive clock and data gating, and by completely redesigning the micro-architecture. We also present original clock gating techniques: pre-computed clock gating. To validate these techniques, simulation results are compared with other realizations of the same microcontroller. It shows that gating techniques can achieve good performances. All comparison results are then validated by measures achieved on a chip prototype.

Assessing the Soft Error Rate of Digital Architectures Devoted to Operate in Radiation Environment: A Case Studied

The effects of transient bit flips on the operation of processor based architectures is investigated through fault injection experiments performed in the hardware itself by means of the interruption mechanism. Such an approach is based on the execution, as the consequence of an interruption signal assertion, of pieces of code called CEU (Code Emulating Upsets), asynchronously downloaded in a suitable memory area. This paper focuses in the methodology followed to set-up CEU injection experiments on a digital architecture, illustrating it main steps by means of a studied case: the 80C51 microcontroller. Results obtained from automated fault injection sessions performed using the capabilities of a devoted test system, will point out the capabilities and limitations of the studied approach.

Predicting error rate for microprocessor-based digital architectures through C.E.U. (Code Emulating Upsets) injection

This paper investigates an approach to study the effects of upsets on the operation of microprocessor-based digital architectures. The method is based on the injection of bit-flips, randomly in time and location by using the capabilities of typical application boards. Experimental results, obtained on programs running on two different digital boards, built around an 80C51 microcontroller and a 320C50 Digital Signal Processor, illustrate the potentialities of this new strategy.