16-bit Research Articles

Optimized One-Dimensional SQIsign Verification on Intel and Cortex-M4

SQIsign is a well-known post-quantum signature scheme due to its small combined signature and public-key size. However, SQIsign suffers from notably long signing times, and verification times are not short either. To improve this, recent research has explored both one-dimensional and two-dimensional variants of SQIsign, each with distinct characteristics. In particular, SQIsign2D’s efficient signing and verification times have made it a focal point of recent research. However, the absence of an optimized one-dimensional verification implementation hampers a thorough comparison between these different variants. This work bridges this gap in the literature: we provide a state-of-the-art implementation of one-dimensional SQIsign verification, including novel optimizations. We report a record-breaking one-dimensional SQIsign verification time of 8.55 Mcycles on a Raptor Lake Intel processor, closely matching SQIsign2D on the same processor. For uncompressed signatures, the signature size doubles and we verify in only 5.6 Mcycles. Taking advantage of the inherent parallelism available in isogeny computations, we present 5-core variants that can go as low as 1.3 Mcycles. Furthermore, we present the first implementation that supports both 32-bit and 64-bit processors. It includes optimized assembly code for the Cortex-M4 and has been integrated with the pqm4 project. Our results motivate further research into one-dimensional SQIsign, as it boasts unique features among isogeny-based schemes.

Paving the Way for SQIsign: Toward Efficient Deployment on 32-bit Embedded Devices

The threat of quantum computing has spurred research into post-quantum cryptography. SQIsign, a candidate submitted to the standardization process of the National Institute of Standards and Technology, is emerging as a promising isogeny-based signature scheme. This work aimed to enhance SQIsign’s practical deployment by optimizing its low-level arithmetic operations. Through hierarchical decomposition and performance profiling, we identified the ideal-to-isogeny translation, primarily involving elliptic curve operations, as the main bottleneck. We developed efficient 32-bit finite field arithmetic for elliptic curves, such as basic operations, like addition with carry, subtraction with borrow, and conditional move. We then implemented arithmetic operations in the Montgomery domain, and extended these to quadratic field extensions. Our implementation offers improved compatibility with 32-bit architectures and enables more fine-grained SIMD acceleration. Performance evaluations demonstrated the practicality in low-level operations. Our work has potential in easing the development of SQIsign in practice, making SQIsign more efficient and practical for real-world post-quantum cryptographic applications.

Implementation of home OSAHS screening device based on sleep sounds

Obstructive Sleep Apnea-Hypopnea Syndrome (OSAHS) is a common chronic sleeping respiratory condition. Screening for OSAHS approaches based on sleep breathing sounds has received much attention since it can provide fully noncontact monitoring at home. Deploying a diagnostic sound-based OSAHS system on a smartphone not only interferes with regular phone use but may also pose privacy problems, as well as suffer from decreasing accuracy owing to device variances. This work describes a local OSAHS monitoring system implementation designed for a dedicated device to estimate the apnea-hypopnea index and screening for OSAHS while doing away with concerns about the abovementioned issue. The OSAHS screening system is deployed on a Kendryte K510 (Canaan Inc.), a low-power RISC-V 64-bit CPU that has 2.5 TFLOPS, to analyze sleep breath sounds in a 9-s window. The design results are relatively low-cost and efficient for screening severe OSAHS. The equipment can be further used as a platform to evaluate the performance of the OSAHS diagnosis model.

FPGA-Based Numerical Simulation of the Chaotic Synchronization of Chua Circuits

The objective of this work was to design and implement a system based on reconfigurable hardware as a study tool for the synchronization of chaotic circuits. Mathematical models were established for one circuit, two synchronized, and multiple synchronized Chua circuits. An ordinary differential equation solver was developed applying Euler’s method using the Verilog hardware description language and synthesized on a Spartan 3E FPGA (Field-Programmable Gate Array) equipped with a 32-bit RISC processor, 64 MB of DDR SDRAM, and 4 Mb of PROM. With a step size of 0.005 and a total of 10,000 iterations, the state equations for one and three Chua circuits were solved at a time of 0.2 ms and a frequency of 50 Mhz. The logical resources used by the system did not exceed 4%. To verify the operation, a numerical simulation was carried out using the Octave V9.1.0 calculation software on an Intel(R) Core i7-9750H CPU 2.59 GHz computer, obtaining the same results but in a time of 493 ms and 3.177 s for one and three circuits, respectively.

Double-Ended Bit-Stealing for Algebraic Data Types

Algebraic data types are central to the development and evaluation of most functional programs. It is therefore important for compilers to choose compact and efficient representations of such types, in particular to achieve good memory footprints for applications. Algebraic data types are most often represented using blocks of memory where the first word is used as a so-called tag, carrying information about the constructor, and the following words are used for carrying the constructor's arguments. As an optimisation, lists are usually represented more compactly, using a technique called bit-stealing, which, in its simplest form, uses the word-alignment property of pointers to byte-addressed allocated memory to discriminate between the nil constructor (often represented as 0x1) and the cons constructor (aligned pointer to allocated pair). Because the representation supports that all values can be held uniformly in one machine word, possibly pointing to blocks of memory, type erasure is upheld. However, on today's 64-bit architectures, memory addresses (pointers) are represented using only a subset of the 64 bits available in a machine word, which leave many bits unused. In this paper, we explore the use, not only of the least-significant bits of pointers, but also of the most-significant bits, for representing algebraic data types in a full ML compiler. It turns out that, with such a particular utilisation of otherwise unused bits, which we call double-ended bit-stealing, it is possible to choose unboxed representations for a large set of data types, while still not violating the principle of uniform data-representations. Examples include Patricia trees, union-find data structures, stream data types, internal language representations for types and expressions, and mutually recursive ASTs for full language definitions. The double-ended bit-stealing technique is implemented in the MLKit compiler and speedup ranges from 0 to 26 percent on benchmarks that are influenced by the technique. For MLKit, which uses abstract data types extensively, compilation speedups of around 9 percent are achieved for compiling MLton (another Standard ML compiler) and for compiling MLKit itself.

IEDCL: Streamlined, False-Error-Free Error Detection and Correction Scheme in a Near-Threshold Enabled 32-bit Processor

iEDCL: Streamlined, False-Error-Free Error Detection and Correction Scheme in a Near-Threshold Enabled 32-bit Processor

Implementation of a Multiclocked Pipelined Processor Based on RISc-V using RV321

This study's primary objective is to create a 32-bit pipelined processor based on the open-source RV32I Version 2.0 RISC-V ISA that operates across several clock domains. A processor known as a RISC (Reduced Instruction Set Computer) employs less hardware than a CISC (Complex Instruction Set Computer) in order to reduce the complexity of the instruction set and accelerate the execution time per instruction. In addition, we built this processor with five pipelining layers, which allows for concurrent processing of instructions. All of the procedures are thoroughly explained, supported with the required block diagrams. To guarantee that variable delays, such as clock skew and meta-stability, are avoided inside the stage pipeline registers, multiple clock domains using two clock sources are employed.

Wearable Processors Architecture: A Comprehensive Analysis of 64-bit ARM Processors

Wearable Processors Architecture: A Comprehensive Analysis of 64-bit ARM Processors

An energy-efficient 32-bit bit-parallel superconducting SFQ specialized processor

As the demand for energy efficiency rises, researchers are increasingly prioritizing the quest for energy-efficient chip design. Superconducting SFQ circuit technology has garnered attention due to its ultra-high speed and low power consumption characteristics. In this paper, we propose a layout method called Maximum Operating Frequency Constraint (MOFC) for SFQ circuit design. Using this method, we demonstrated a 32-bit bit-parallel string-matching processor fabricated based on SIMIT-Nb03P technology, which holds practical value. The MOFC method focuses on achieving high bit-width processor design within constrained area cost in SFQ circuits, contributing to less energy consumption. To the best of our knowledge, this represents the first demonstrated instance of a superconducting SFQ chip achieving successful internal 32-bit data parallel processing. Our chip has been fabricated and tested, revealing not only its capability for 32-bit bit-parallel processing at a high speed of 12 GHz but also its achievement of an energy efficiency ratio of up to 251 GOPS/W.

DEVELOPMENT OF THE DEVICE FOR CONTROLLING AND MEASURING THE SUPPLY OF WORKING GAS FOR LABORATORY TESTING OF THE ELECTRIC PROPULSION THRUSTERS

The object of the research is a device for measuring, controlling, and indicating the flow rate of working gas during laboratory testing of electric propulsion systems for space applications. The problem lies in the need to ensure high accuracy in controlling and measuring the flow rates of working gas for such devices. The obtained results include: analysis of existing industrial flow meters that could be used in development; proposed structural and functional diagrams of the device; experimental investigations into the accuracy of the developed device. Based on the analysis of parameters of the most common flow meters for development, the Bronkhorst F-201CV-100-AAD-22-V regulator was selected. Based on the selected regulator, a device was developed with a 32-bit ARM architecture. This architecture provides for the use of floating-point calculations, easy reprogramming of the device, and fast indication of values displayed on the indicator. The device features galvanic isolation between the control bus and the UART port of the microcontroller. The device allows for regulation, measurement, and indication of the flow rate of working gas into the anode block and hollow cathode during testing of Hall thrusters. Using the device allows for recommendations regarding the design of onboard systems for supplying working fluid to electric rocket propulsion systems. Based on the presented development and conducted research, laboratory prototypes of the devices were manufactured. The measurement error throughout the entire range of working gas flow rates does not exceed 0.7%. The overall error of the stand control and measurement system for working gas flow rates is up to 3%. The developed device provides measurement accuracy that satisfies the developers of electric propulsion systems.

Embedded machine learning-based road conditions and driving behavior monitoring

Car accident rates have increased in recent years, resulting in losses in human lives, properties, and other financial costs. An embedded machine learning-based system is developed to address this critical issue. The system can monitor road conditions, detect driving patterns, and identify aggressive driving behaviors. The system is based on neural networks trained on a comprehensive dataset of driving events, driving styles, and road conditions. The system effectively detects potential risks and helps mitigate the frequency and impact of accidents. The primary goal is to ensure the safety of drivers and vehicles. Collecting data involved gathering information on three key road events: normal street and normal drive, speed bumps, circular yellow speed bumps, and three aggressive driving actions: sudden start, sudden stop, and sudden entry. The gathered data is processed and analyzed using a machine learning system designed for limited power and memory devices. The developed system resulted in 91.9% accuracy, 93.6% precision, and 92% recall. The achieved inference time on an Arduino Nano 33 BLE Sense with a 32-bit CPU running at 64 MHz is 34 ms and requires 2.6 kB peak RAM and 139.9 kB program flash memory, making it suitable for resource-constrained embedded systems.

64-비트 ARMv8 프로세서 상에서의 개선된 병렬 ARIA 최적화 구현

64-비트 ARMv8 프로세서 상에서의 개선된 병렬 ARIA 최적화 구현

Mixed-Input Residual Network for Air Temperature Forecasting by Low-Power Embedded Devices

Accuracy and model compactness are essential requirements for weather forecasting models designed for operation on low-power embedded devices. This study developed Mixed-Input Residual Network (MIRNet), a compact temperature-forecasting deep neural network model. MIRNet integrates stacked bidirectional long short-term memory layers using concatenated 1-dimensional and 2-dimensional convolutional layers to improve model accuracy. MIRNet was trained and tested on two datasets: one, IfeData, comprising historical weather data from Ile-Ife, Nigeria and the other a standard weather forecasting dataset called the Jena dataset. Training was carried out using 100 epochs of data partitioned in the standard 80:20 ratio, with an adaptable learning rate strategy. The model was tested for Nth-hour-ahead prediction for 1N24; where N are natural numbers, and performance quantified using metrics such as mean absolute percentage error (MAPE) and mean square error (MSE). The model was also implemented on a Raspberry Pi 4 device with a 1.8 GHz 64-bit quad-core ARM Cortex-A72 processor. The model achieved a MSE of 1.00 x 10-3 on the IfeData dataset, and 1.23x10-4 on the Jena dataset for 1-hour ahead forecasting. This is currently the best verifiable result achieved on the Jena dataset by any prediction model globally. For Nth hour ahead forecasting, MIRNet achieved an MSE generally below 2.0x10-3 for all values of N on the standard Jena dataset. The MSE of MIRNet for N-sequential 1-hour ahead and single Nth hour predictions using the Jena dataset reveal quadratic and linear relationships with N respectively. The model compares favourably with existing models for multi-hour predictions. The developed model is compact and has good forecasting properties.

Design of a Linear Layer Optimised for Bitsliced 32-bit Implementation

The linear layer of block ciphers plays an important role in their security In particular, ciphers designed following the wide-trail strategy use the branch number of the linear layer to derive bounds on the probability of linear and differential trails. At FSE 2014, the LS-design construction was introduced as a simple and regular structure to design bitsliced block ciphers. It considers the internal state as a bit matrix, and applies alternatively an identical S-Box on all the columns, and an identical L-Box on all the lines. Security bounds are derived from the branch number of the L-Box.In this paper, we focus on bitsliced linear layers inspired by the LS-design construction and the Spook AEAD algorithm. We study the construction of bitsliced linear transformations with efficient implementations using XORs and rotations (optimized for bitsliced ciphers implemented on 32-bit processors), and a high branch number. In order to increase the density of the activity patterns, the linear layer is designed on the whole state, rather than using multiple parallel copies of an L-Box. Our main result is a linear layer for 128-bit ciphers with branch number 21, improving upon the best 32-bit transformation with branch number 12, and the one of Spook with branch number 16.

Predictive controllers for synchronous reluctance motor drive systems

This paper proposes the design and implementation of predictive controllers for synchronous reluctance motor drive systems to enhance their dynamic responses. The predictive speed and current controllers in this paper are designed in systematic procedures. The predictive speed controller is implemented by using Laguerre function procedure. The Laguerre function is used to simplify the algorithm and to minimize the execution time of the digital signal processor. For predictive current controller, a finite control set method improves the current tracking ability. The measured currents are used to predict the future phase-current based on the motor model. The optimal control inputs of both predictive controllers are determined by using a cost function minimization method. Experimental results show the proposed drive system provides a wide adjustable speed range, from 2 r/min to 1800 r/min. It has better performance than a proportional-integral (PI) controller including fast rise time, which is 0.9 second, small steady state error, which is 0.32 r/min, and small current ripples. A 32-bit floating-point digital signal processor, TMS-320-F-28335 DSP, is employed to implement the control algorithms.

Implementation of 64-Bit RISC Processor Using Vedic Multiplier

Abstract: In this project, 64 bit RISC processor designed with Vedic multiplier design. Reduced Instruction Set Computer (RISC) is a design which presents better performances, higher speed of operation and favors the smaller and simpler set of instructions. In addition to multiplier which is implemented using vedic mathematics we are also proposing an adder which is mux- based full adders for building higher bit adders in an area and speed efficient which is implemented in addition as well as for compression in vedic mathematic to obtain the output. A 64 bit RISC processor designed in this paper is capable of executing more number of instructions with simple design, using the Verilog Hardware Description Language (HDL) and the design is simulated in the Xilinx Vivado 2018.3. The main achievement in this work is that the multiplier unit in Arithmetic and Logic Unit (ALU) and Multiplier and Accumulator (MAC) is implemented using Vedic Sutras. The main principle used in Vedic mathematics is to reduce the typical calculation of conventional mathematics to very simple one and hence reduce the overall computational complexity. Vedic Multiplier design is based on “Urdhva Triyakbhyam” which is among the 16 Vedic Sutras and MUX-Based Full Adders The proposed RISC processor is very simple and capable of executing 14 instructions. The achievement in this work is that savings in power in case of MAC and ALU is achieved compared to conventional ALU and MAC respectively. Also the delay is reduced in MAC and ALU in comparison with conventional ALU and MAC correspondingly. These Vedic MAC and ALU are then integrated with other blocks in processor and 64-bit Vedic processor is developed. This reduces the delay and saves area compared to conventional processor. Hence the improvement in speed of operation, and less area utilization are the key features of designed RISC processor.

NLU-V: A Family of Instruction Set Extensions for Efficient Symmetric Cryptography on RISC-V

Cryptographic primitives nowadays are not only implemented in high-performance systems but also in small-scale systems, which are increasingly powered by open-source processors, such as RISC-V. In this work, we leverage RISC-V’s modular base instruction set and architecture to propose a generic instruction set extension (ISE) for symmetric cryptography. We adapt the work from Engels et al. in ARITH’13, the non-linear/linear instruction set extension (NLU), which presents a generic hardware/software co-design solution for efficient symmetric crypto implementations through a hardware unit extending the 8-bit AVR instruction set. These new instructions realize non-linear and linear layers, which are widely used to implement the block ciphers in symmetric cryptography. Our proposal modifies and extends the NLU instructions to a 32-bit RISC-V architecture; hence, we call the proposed ISE ‘NLU-V’. The proposed architecture is integrated into the open-source RISC-V implementation ‘Icicle’ and synthesized on a Xilinx Kintex-7 XC7K160T FPGA. The area overhead for the proposed NLU-V ISE is 1088 slice registers and 4520 LUTs. As case studies, the PRESENT and AES block ciphers are implemented using the new ISE on RISC-V in assembly. Our evaluation metric to showcase the performance gain, Z ‘time-area-product (TAP)’ (the execution time in clock cycles times code memory consumption), reflects the impact of the proposed family of instructions on the performance of the cipher implementations. The simulations show that the NLU-V achieves 89% gain for PRESENT and 68% gain for AES. Further, the NLU-V requires 44% less lines of code for the PRESENT and 23% less for the AES implementation.

Teaching computer architecture by designing and simulating processors from their bits and bytes.

Teaching computer architecture (Comp-Arch) courses in undergraduate curricula is becoming more of a challenge as most students prefer software-oriented courses. In some computer science/engineering departments, Comp-Arch courses are offered without the lab component due to resource constraints and differing pedagogical priorities. This article demonstrates how students working in teams are motivated to study the Comp-Arch course and how instructors can increase student motivation and knowledge by taking advantage of hands-on practices. The teams are asked to design and implement a 16-bit MIPS-like processor with constraints as a specific instruction set, and limited data and instruction memory. Student projects include following three phases, namely, design, desktop simulator implementation, and verification using hardware description language (HDL). In the design phase, teams develop their Comp-Arch to implement specified instructions. A range of designs resulted, e.g., (a) a processor with extensive user-defined instructions resulting in longer cycle times (b) a processor with a minimal instruction set but with a faster clock cycle time. Next, teams developed a desktop simulator in any programming language to execute instructions on the architecture. Finally, students engage in Verilog Hardware Description Language (HDL) projects to simulate and verify the data-path designed during the initial phase. Student feedback and their current understanding of the project were collected through a questionnaire featuring varying Likert scale questions, some with a ten-point scale, and others with a five-point scale. Results of the survey show that the hands-on approach increases students' motivation and knowledge in the Comp-Arch course, which is centered around computer system design principles. This approach can also be effectively extended to related courses, such as Microprocessor Design, which delves into the intricacies of creating and implementing microprocessors or central processing units (CPUs) at the hardware level. Furthermore, the present study demonstrates that interactions, specifically through peer reviews and public presentations, between students in each phase increases their knowledge and perspective on designing custom processors.

Design and Evaluation of Open-Source Soft-Core Processors

The advantage of FPGAs lies in their ability to implement a fully hardware solution for interfacing with various input/output (I/O) devices. Each block can work in parallel with all the others, simplifying the satisfaction of timing constraints. However, this hardware utilization consumes FPGA resources that could otherwise be allocated to the primary project. An alternative involves employing a small “soft-core” processor to implement I/O in software. With the goal of designing and evaluating a new tiny soft-core processor optimized for FPGA resources in I/O, a novel processor named Baby8 is developed. It is an 8-bit CISC soft-core processor optimized for reduced FPGA resources, including program size for 8-bit applications. The number of instructions is not large, but any instruction can access arbitrary memory locations. The performance and resource utilization of the newly designed processor are evaluated and compared with a variety of other soft-core processors. The results demonstrate its competitive performance, achieving an average maximum clock frequency of approximately 57 MHz and a power consumption of around 2 mW. Furthermore, it conserves nearly half of the FPGA resources in implementation.

Design of RISCV processor using verilog

The main goal of this paper is to develop a 32-bit pipelined processor with several clock domains based on the RISCV (open source RV32I Version 2.0) ISA. To minimize the complexity of the instruction set and speed up the execution time per instruction, a RISC (Reduced Instruction Set Computer) processor that uses less hardware than a CISC (Complex Instruction Set Computer) is used. Furthermore, this paper constructed this processor with five levels of pipelining with the aid of necessary block diagrams, and all of the processes are well described. In this paper, a RISCV processor is designed and simulated using Verilog. The design of the RISCV processor provides an alternative for software and hardware design to the computer designers as it provides free and open instruction set architecture (ISA). Besides, the designed RISCV processor will be using 5-stage pipeline techniques to improve the overall performance of the processor. This system is started by implementing several main modules, such as alu, aludec, maindec, imem, dmem, regfile, pc_mux, result_mux, pipeline register (IF/ID, ID/IEx, IEx/IMem, and IMem/IW), forwardMuxA, and forwardMuxB. Besides, a hazard unit is implemented into the design to mitigate hazard conditions. The functionality of these modules was simulated and verified by using Xilinx Vivado software.