Ultra High Definition Research Articles

New Driving Structure to Increase Pixel Charging Ratio for UHD TFT-LCDs With High Frame Rate

This paper proposes a new driving structure of the thin-film transistor liquid crystal display (TFT-LCD) for use in notebook displays with ultra-high definition (UHD) and a high frame rate. The proposed pixel circuit improves the pixel charging ratio by reducing the RC loadings of the data lines and extending the available row-line time for pixel charging. A new gate driver circuit that generates two output waveforms in a single stage is presented to reduce the cost and occupied layout area of gate driver ICs, enabling the realization of high-resolution displays with a narrow bezel. To verify the feasibility of the proposed driving structure, a 12.3-inch panel with UHD (3840 × 2160) and a frame rate of 120 Hz is fabricated. Experimental results demonstrate that the proposed driving structure yields a measured pixel charging ratio of more than 97.09% for a heavy loading pattern with a gray level of 255. Following an accelerated lifetime test, the measured waveforms of the proposed gate driver circuit are stable without any malfunction, demonstrating its high reliability. Therefore, the proposed driving structure and the gate driver circuit are highly suitable for use in UHD TFT-LCD notebook applications.

E-Render: Enabling UHD-Quality Cloud Gaming Through Edge Rendering

Cloud gaming services enable users to enjoy various high-quality computer games without installing them in their devices which may have poor resources. However, it consumes high bandwidth in backbone networks as game videos have to be constantly streamed to client devices, which can be a hindering factor for providing Ultra High Definition (UHD)-quality cloud gaming services whose demands are ever increasing. In this paper, we present a novel cloud gaming architecture, <i>E-Render</i>, in which the graphics engine is separated from the cloud game server and is deployed in the edge for rendering. In the architecture, since video frames are streamed from the edge server to the client device via highbandwidth subscriber networks, we can greatly save the backbone network bandwidth. To realize it, however, we need to effectively reduce the amount and latency of graphics commands transfer from the game engine in the cloud to the graphics engine in the edge server. E-render solves the problem by using novel techniques including multi-granular command deduplication and asynchronous buffer binding. We implement a prototype cloud gaming platform based on the E-Render architecture, and evaluate its performance using four real world games. The evaluation results confirm that E-Render can provide UHD-quality cloud gaming services.

AVQBits—Adaptive Video Quality Model Based on Bitstream Information for Various Video Applications

The paper presents <i>AV QBits</i>, a versatile, bitstream-based video quality model. It can be applied in several contexts such as video service monitoring, evaluation of video encoding quality, of gaming video QoE, and even of omnidirectional video quality. In the paper, it is shown that <i>AV QBits</i> predictions closely match video quality ratings obained in various subjective tests with human viewers, for videos up to 4K-UHD resolution (Ultra-High Definition, 3840 x 2180 pixels) and framerates up 120 fps. With the different variants of <i>AV QBits</i> presented in the paper, video quality can be monitored either at the client side, in the network or directly after encoding. The no-reference <i>AV QBits</i> model was developed for different video services and types of input data, reflecting the increasing popularity of Video-on-Demand services and widespread use of HTTP-based adaptive streaming. At its core, <i>AV QBits</i> encompasses the standardized ITU-T P.1204.3 model, with further model instances that can either have restricted or extended input information, depending on the application context. Four different instances of <i>AV QBits</i> are presented, that is, a Mode 3 model with full access to the bitstream, a Mode 0 variant using only metadata such as codec type, framerate, resoution and bitrate as input, a Mode 1 model using Mode 0 information and frame-type and -size information, and a Hybrid Mode 0 model that is based on Mode 0 metadata and the decoded video pixel information. The models are trained on the authors&#x2019; own AVT-PNATS-UHD-1 dataset described in the paper. All models show a highly competitive performance by using AVT-VQDB-UHD-1 as validation dataset, e.g., with the Mode 0 variant yielding a value of 0.890 Pearson Correlation, the Mode 1 model of 0.901, the hybrid no-reference mode 0 model of 0.928 and the model with full bitstream access of 0.942. In addition, all four <i>AV QBits</i> variants are evaluated when applying them out-of-the-box to different media formats such as 360&#x00B0; video, high framerate (HFR) content, or gaming videos. The analysis shows that the ITU-T P.1204.3 and Hybrid Mode 0 instances of <i>AV QBits</i> for the considered use-cases either perform on par with or better than even state-of-the-art full reference, pixel-based models. Furthermore, it is shown that the proposed Mode 0 and Mode 1 variants outperform commonly used no-reference models for the different application scopes. Also, a long-term integration model based on the standardized ITU-T P.1203.3 is presented to estimate ratings of overall audiovisual streaming Quality of Experience (QoE) for sessions of 30 s up to 5 min duration. In the paper, the <i>AV QBits</i> instances with their per-1-sec score output are evaluated as the video quality component of the proposed long-term integration model. All <i>AV QBits</i> variants as well as the long-term integration module are made publicly available for the community for further research.

Modeling Perceived Quality on 8K VVC Video Under Various Screen Sizes and Viewing Distances

Perceptual video quality considerably affects the quality of experience (QoE) of watching television (TV) broadcasts. Viewing conditions, such as the screen size and viewing distance, impact the perceived quality. We performed subjective evaluation experiments on 8K (7,680×4,320) ultra-high definition (UHD) compressed videos under seven viewing conditions (combinations of 31.5-, 55-, and 85-inch displays and 0.75, 1.5, and 3.0 H (times of screen height) of viewing distance). Distorted videos compressed by the versatile video coding (VVC)/H.266 were used in four types of encoding resolution, from 2K (1,920×1,080) to 8K, at a wide bitrate settings range of 3–80 Mbps. We derived a simple regression equation predicting the mean opinion score (MOS) using the hierarchical linear model (HLM), investigating the factors influencing subjective video quality. In this equation, MOS is expressed as a linear combination of terms including intercept and bitrate associated with sequence and encoding resolution, screen size, and viewing distance; it indicates that the smaller the screen, or the further the viewing distance, the fewer artifacts are perceived, as following empirical rules. Furthermore, we confirmed that the derived model is accurate as the Pearson linear and Spearman rank order correlation coefficients between predicted and actual MOS values were more than 0.97.

Under-Display Camera Image Enhancement via Cascaded Curve Estimation.

The new trend of full-screen devices encourages manufacturers to position a camera behind a screen, i.e., the newly-defined Under-Display Camera (UDC). Therefore, UDC image restoration has been a new realistic single image enhancement problem. In this work, we propose a curve estimation network operating on the hue (H) and saturation (S) channels to perform adaptive enhancement for degraded images captured by UDCs. The proposed network aims to match the complicated relationship between the images captured by under-display and display-free cameras. To extract effective features, we cascade the proposed curve estimation network with sharing weights, and we introduce a spatial and channel attention module in each curve estimation network to exploit attention-aware features. In addition, we learn the curve estimation network in a semi-supervised manner to alleviate the restriction of the requirement for amounts of labeled images and improve the generalization ability for unseen degraded images in various realistic scenes. The semi-supervised network consists of a supervised branch trained on labeled data and an unsupervised branch trained on unlabeled data. To train the proposed model, we build a new dataset comprised of real-world labeled and unlabeled images. Extensive experiments demonstrate that our proposed algorithm performs favorably against state-of-the-art image enhancement methods for UDC images in terms of accuracy and speed, especially on ultra-high-definition (UHD) images.

Unified FPGA Design for the HEVC Dequantization and Inverse Transform Modules

As the newest standard, the High Efficiency Video Coding (HEVC) is specially designed to minimize the bitrate for video data transfer and to support High Definition (HD) and ULTRA HD video resolutions at the cost of increasing computational complexity relative to earlier standards like the H.264. Therefore, real-time video decoding with HEVC decoder becomes a challenging task. However, the Dequantization and Inverse Transform (DE/IT) are one of the computationally intensive modules in the HEVC decoder which are used to reconstruct the residual block. Thus, in this paper, a unified hardware architecture is proposed to implement the HEVC DE/IT module for all Transform Unit (TU) block size, including 4 × 4, 8 × 8, 16 × 16 and 32 × 32. This architecture is designed using the High-Level Synthesis (HLS) and the Low-Level Synthesis (LLS) methods in order to compare and determine the best method to implement in real-time the DE/IT module. In fact, the C/C++ programming language is used to generate an optimized hardware design for DE/IT module through the Xilinx Vivado HLS tool. On the other hand, the LLS hardware architecture is designed by the VHSIC Hardware Description language (VHDL) and using the pipeline technique to decrease the processing time. The experimental results on the Xilinx XC7Z020 FPGA show that the LLS design increases the throughput in term of frame rate by 80% relative to HLS design with a 4.4% increase in the number of Look-Up Tables (LUTs). Compared with existing related works in literature, the proposed architectures demonstrate significant advantages in hardware cost and performance improvement.

A Survey on Mobile Edge Computing for Video Streaming: Opportunities and Challenges

5G communication brings substantial improvements in the quality of service provided to various applications by achieving higher throughput and lower latency. However, interactive multimedia applications (e.g., ultra high definition video conferencing, 3D and multiview video streaming, crowd-sourced video streaming, cloud gaming, virtual and augmented reality) are becoming more ambitious with high volume and low latency video streams putting strict demands on the already congested networks. Mobile Edge Computing (MEC) is an emerging paradigm that extends cloud computing capabilities to the edge of the network i.e., at the base station level. To meet the latency requirements and avoid the end-to-end communication with remote cloud data centers, MEC allows to store and process video content (e.g., caching, transcoding, pre-processing) at the base stations. Both video on demand and live video streaming can utilize MEC to improve existing services and develop novel use cases, such as video analytics, and targeted advertisements. MEC is expected to reshape the future of video streaming by providing ultra-reliable and low latency streaming (e.g., in augmented reality, virtual reality, and autonomous vehicles), pervasive computing (e.g., in real-time video analytics), and blockchain-enabled architecture for secure live streaming. This paper presents a comprehensive survey of recent developments in MEC-enabled video streaming bringing unprecedented improvement to enable novel use cases. A detailed review of the state-of-the-art is presented covering novel caching schemes, optimal computation offloading, cooperative caching and offloading and the use of artificial intelligence (i.e., machine learning, deep learning, and reinforcement learning) in MEC-assisted video streaming services.

Ultrahigh Definition Two-Piece Can Decoration

Ultrahigh Definition Two-Piece Can Decoration

Progressive Joint Low-Light Enhancement and Noise Removal for Raw Images.

Low-light imaging on mobile devices is typically challenging due to insufficient incident light coming through the relatively small aperture, resulting in low image quality. Most of the previous works on low-light imaging focus either only on a single task such as illumination adjustment, color enhancement, or noise removal; or on a joint illumination adjustment and denoising task that heavily relies on short-long exposure image pairs from specific camera models. These approaches are less practical and generalizable in real-world settings where camera-specific joint enhancement and restoration is required. In this paper, we propose a low-light imaging framework that performs joint illumination adjustment, color enhancement, and denoising to tackle this problem. Considering the difficulty in model-specific data collection and the ultra-high definition of the captured images, we design two branches: a coefficient estimation branch and a joint operation branch. The coefficient estimation branch works in a low-resolution space and predicts the coefficients for enhancement via bilateral learning, whereas the joint operation branch works in a full-resolution space and progressively performs joint enhancement and denoising. In contrast to existing methods, our framework does not need to recollect massive data when adapted to another camera model, which significantly reduces the efforts required to fine-tune our approach for practical usage. Through extensive experiments, we demonstrate its great potential in real-world low-light imaging applications.

AN EFFICIENT ADAPTATION OF UHD VIDEO STREAMING OVER INTERNET

The main challenge of multimedia applications is how to transmission the Ultra-High Definition (UHD) video streaming in real time over the internet. The real time video streaming suffer from difficulties to be flexible and efficiency cause the wide variation of the available internet bandwidth. To avoid the problems that introduces with internet, in this work the HEVC with required video network adaptive streaming are proposed and tested using different six levels of three UHD video (4K, FHD, 720p, 4CIF, CIF and QCIF). From different experiments that applied find the optimal configuration of H.265 encoding features for six levels to obtain the required PSNR with range (32-38 dB). The important part in this project is a controller that worked incorporate with the encoder (H.265) to obtain the video streaming adaptation on the available bandwidth of the channel. The controller continuously reads the status of channel buffer, then choosing the proper level of video to be transmitted over the channel. The work architecture is content two parts: First, the H.265 codec that apply on the three raw videos with optimal parameters configuration to compress them and get videos with lower bit rate and acceptable quality. Second, the compressed videos, based to controller.....

Research on the Application of 4K+5G Technology for UHD Live TV: Taking China Media Group as an Example

This paper systematically reviews the development history of 4K UHD TV in China, analyzes the innovative application of 4K+5G technology in the field of UHD TV live broadcast, and analyzes its characteristics and advantages. Taking the UHD TV broadcast by The China Media Group(CMG) using 4K+5G technology as an example, this paper analyzes the role of 4K+5G technology in promoting the reform of radio and television programs and its future development direction, so as to provide references for the industry.

DVL2021: An ultra high definition video dataset for perceptual quality study

This paper describes an ultra high definition (UHD) video dataset named DVL2021 for the perceptual study of video quality assessment (VQA). To our knowledge, DVL2021 is the first authentically distorted 4K (3840 × 2160) UHD video quality dataset. The dataset contains 206 versatile 4K UHD video sequences, which are all collected in in-the-wild scenarios. Each sequence is captured at 50 frames per second (fps), stored in raw 10-bit 4:2:0 YUV format, and has a duration of 10 s. Following the subjective evaluation method of TV image quality granted by ITU-R BT.500-13, 32 unique participants take part in the manual annotation process, whose ages are from teenage to sixties (32.7 years old on average). DVL2021 has the following merits: (1) enormous variety of video contents, (2) captured by different types of cameras, (3) complex types and multiple levels of authentic distortion, (4) broadly distributed temporal/spatial information, and (5) a wide spectrum of mean opinion scores (MOS) distribution. Furthermore, we conduct a benchmark experiment by evaluating several mainstream VQA methods on DVL2021. The baseline results are higher than 0.75 in Spearman’s rank order correlation coefficient (SROCC) metric. Our study provides a basis for the UHD VQA problem. DVL2021 is publicly available at https://github.com/GZHU-DVL/DVL2021.

Steganalysis attacks resilient, imperceptible, blind, and keyed image hiding in ultra HD 4K video

ABSTRACT A novel data hiding approach is being proposed in this article, camouflaging secret data within a very high-quality video object. The proposed algorithm utilizes Discrete Wavelet Transform (DWT) and Discrete Cosine Transform (DCT) to hide image data, preprocessed using Arnold Transform. The novelty of this approach lies in the combination of five factors, which are – use of very high-resolution Ultra HD 4 K video as a cover object; Use of DCT coefficient in Scene Change Detection to identify cover frame; Scrambling the secret image by Arnold Transformation; Use of DCT-DWT in embedding and extraction process to that hide data in the blue plane of the RGB frame; and lastly, use of three different keys for data hiding to secure the proposed method against attacks, by adhering the Kerckhoff’s principle of a cryptosystem. Several quality metrics like Structural Content, Peak Signal-to-Noise Ratio, Normalized Cross-Correlation, Average Difference, Maximum Difference, and Normalized Absolute Error have been calculated to validate the imperceptibility. This method has also been validated against different steganalysis attacks like random cropping, rotating, resizing, noise addition, filtering, histogram attack, and lastly, compared with existing data hiding methods to prove superiority.

Defect Engineering for High-Performance Microscale Light-Emitting Diode Devices By Surface Passivation

Microscale light-emitting diodes (µLEDs) are regarded as the cornerstone of next-generation display technology to meet the personalized demands of advanced applications, such as mobile phones, wearable watches, virtual/augmented reality, micro-projectors, and ultrahigh definition TVs. However, the ratio of the sidewall area to the emitting area increases as the pixel size of µLEDs becomes small, which can increase the possibility of the non-radiative recombination process near the active layer resulting in a low efficiency of µLEDs. To overcome these issues, in general, a passivation layer such as SiO2, SiNx, and Al2O3 has been applied to passivate dangling bonds near the surface of the sidewall to ruduce surface defects. In addition, heat treatment method has been used for curing the defect sites near the sidewall to maximize the effect of surface passivation; however, there are few reports on the analysis of curing mechanism considering carrier dynamics and/or devcie performance of µLEDs using various materials of passiation layer.In this regard, we studied the performance of µLEDs depending on the passivation layer (SiO2, SiNx, Al2O3) by considering charge distribution and carrier dynamics near the sidewall region. First, X-ray photoelectron spectroscopy was conducted to investigate what kind of bonds are formed between the atoms. Based on this analysis, we verified oxygen and nitrogen atoms are closely associatted with the amount of passivated states, which also confirmed by capacitance-voltage characteristics via keithley measurment system. In addtion, photnoluminescence (PL) efficiencies depending on the passivation layer were measured to understand the carrier dynamics of µLED devices using temperature-dependent PL measurement system (18–300 K). As a result, PL efficiency of the sample with the passivation layer was enhanced by 15% (SiO2), 6% (SiNx), and 12% (Al2O3) compared to that of the sample without passivation layer, which can be attributed to the removed non-radiatve defects near the sidewall area after passivation. More detailed experimental results and device performance of µLEDs will be presented at the conference.

A high throughput hardware architecture for deblocking filter in HEVC

This paper presents a high throughput hardware architecture for deblocking filter in high efficiency video coding (H.265/HEVC) standard. The architecture uses an efficient hybrid pipelining and parallel processing techniques for intra encoder. A single edge filter is designed to process both horizontal and vertical filtering of pixels one after the other respectively. In our proposed architecture, the video frame is divided into 32×32 blocks and each block is processed by splitting them into blocks of 8×32 pixels in a pipelined manner. Parallel processing is employed for filtering the edges which helped in improving the throughput by decreasing the processing clock cycles. It has been observed that the largest coding tree unit block that the hardware architecture can process is 64 × 64 pixels and can be achieved in 64 clock cycles. Synthesis results of the Verilog design for the proposed architecture using application specific integrated circuit 180 nm standard cell library shows that it consumes 102k 2-input NAND gates and can work at a maximum clock frequency of 250 MHz. The proposed design is capable of supporting 8k ultra high definition video sequences at 322 Frames Per Second (fps) which is the best among the existing present-day architectures.

Design and Implementation of Parallel Bypass Bin Processing for CABAC Encoder

The ever-increasing demand for high-quality digital video requires efficient compression techniques and fast video codecs. It necessitates increased complexity of the video codec algorithms. So, there is a need for hardware accelerators to implement such complex algorithms. The latest video compression algorithms such as High-Efficiency Video Coding (HEVC) and Versatile Video Coding (VVC) have been adopted Context-based Adaptive Binary Arithmetic Coding (CABAC) as the entropy coding method. The CABAC has two main data processing paths: regular and bypass bin path, which can achieve good compression when used with Syntax Elements (SEs) statistics. However, it is highly intrinsic data dependence and has sequential coding characteristics. Thus, it is challenging to parallelize. In this work, a 6-core bypass bin path having high-throughput and low hardware area has been proposed. It is a parallel architecture capable of processing up to 6 bypass bins per clock cycle to improve throughput. Further, the resource-sharing techniques within the binarization and a common controller block have reduced the hardware area. The proposed architecture has been simulated, synthesized, and prototyped on 28 nm Artix 7 Field Programmable Gate Array (FPGA). The implementation of Application Specific Integrated Circuit (ASIC) has been done using 65 nm CMOS technology. The proposed design achieved a throughput of 1.26 Gbin/s at 210 MHz operating frequency with a low hardware area compared to existing architectures. This architecture also supports multi-standard (HEVC/VVC) encoders for Ultra High Definition (UHD) applications.

Field Trials of UHDTV Broadcasting over DTMB-A System

<italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Digital terrestrial television broadcasting (DTTB), the most fundamental infrastructure for audio/video transmission networks, can support multimedia information services, targeting lots of audiences within a wide area in an efficient way. The advanced version of digital television/terrestrial multimedia broadcasting (DTMB-A), one of the second-generation DTTB standards of the International Telecommunication Union, provides higher spectrum efficiency and better transmission reliability compared with DTMB. By adopting a more flexible frame structure, advanced forward error correction coding, and improved constellation mapping, it is confirmed that the transmission capacity of DTMB-A is around 30% higher than that of DTMB under the same conditions carried out in laboratory tests and field trials on DTMB-A. In this paper, the trial network and the measurement results focusing on ultrahigh-definition television (UHDTV, both UHD-1/4K and UHD-2/8K) and the single-frequency network (SFN) are presented in detail. The preliminary work on the Integrated Communications and Broadcasting Network (ICBN) concept using both DTMB-A and fifth-generation (5G) networks for UHDTV delivery is also highlighted</i> .

Efficient video transmission—a critical review of various protocols and strategies

ABSTRACT With the advent of 3D video technology and ultra-high-definition (UHD) displays, traditional video coding methods and network/transport protocols seem to fail. This necessitates optimizations at multiple levels and layers: codec-level, system-level, and different layers in the TCP/IP suite. We critically analyze various protocols at different layers in the TCP/IP suite and compare them for various applications. Moreover, the importance of devising intelligent behavior-based strategies at the server side is highlighted. Furthermore, roles and advantages of cross-layer optimization in video transmission are given. The importance of datagram congestion control protocol (DCCP) in an efficient video transmission in the coming years is unfolded. We demonstrate the importance of devising good strategies at the server side in saving the bandwidth. To the best of the knowledge of the authors, this is the first paper that elaborates on DCCP and its significance for the future. In this article, besides analyzing various protocols and discussing optimizations, etc., the value-added suggestions on how to make improvements at various levels are presented. Thus, this work is a one-stop source of information for researchers working on this topic.

Fast block partitioning scheme for chrominance intra prediction of versatile video coding standard

We present a fast block partitioning scheme for chrominance intra prediction of the Versatile Video Coding (VVC) standard. VVC adopted several innovative tools to improve the coding performance compared with its predecessor standard, enabling the efficient handling of emerging video content such as ultra-high definition (UHD). These coding performance improvements come at the cost of a significant increase in coding complexity, mainly due to the new block partitioning structure called quadtree with nested multi-type tree (QTMT), which can be applied separately for luminance and chrominance components. Thus, this work proposes a scheme focusing on chrominance intra coding, composed of chrominance splitting early termination based on luminance QTMT and fast chrominance split decision based on the sub-block variances. Experimental results demonstrated that the proposed scheme provides 60.03% and 8.18% of chrominance and total encoding time savings, respectively, with a negligible impact of 0.66% in the YUV-BDBR.

High-Speed Column Driver IC Having Buffer Amplifier with Embedded Isolation Switch and Compact Adaptive Biasing for Flat-Panel Displays

A high-speed column driver IC with an area-efficient high-slew-rate buffer amplifier is proposed for use in a large-sized, high-resolution TFT-LCD panel application. In the proposed architecture, explicit isolation switches have been embedded into the buffer amplifier resulting in a fast settling response. The amplifier also has a structure that adjusts the tail current of the input stage using a very compact adaptive biasing. The proposed column driver IC, having the proposed buffer amplifier for driving a 55-inch 4K ultra-high-definition (UHD) TV panel, was fabricated in a 0.18-μm 1.8-V low-voltage, 1.2-μm 9-V medium-voltage, and 1.6-μm 18-V high-voltage CMOS process. The performance evaluation results indicated that 90% and 99.9% falling settling times were improved from 1.947 µs to 0.710 µs (63.5% improvement) and 4.131 µs to 2.406 µs (41.7% improvement), respectively. They also indicated that the layout size of the proposed buffer amplifier was reduced from 5580 μm2 to 4402 μm2 (21.1% reduction).