45nm SOI Technology Research Articles

A Low Power Real-time On-Chip Power Sensor in 45-nm SOI

This paper introduces a real-time on-chip power and temperature sensor for active power management in scaled CMOS technologies. In a distinct departure from earlier power estimation techniques, this sensor measures the voltage drop due to a current load and converts it into pulse counts to get a power estimate in real time. Linear regression is used to estimate load current based on the measured output frequency at a given temperature. The same sensor is also used to estimate temperature in a mode where output time period decreases linearly with temperature. Measurement results show accuracy to within ±1.05 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C for temperature estimation in the range of 22 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C-100 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">°</sup> C and within ±10% of the actual power consumed (for loads ≤ 3.3 mA). Fabricated in 45-nm SOI technology, this power and temperature sensor occupies an area of 140 μm×140μm and has a power overhead of 120 μW at 1.2 V supply.

Novel SEU hardened PD SOI SRAM cell

A novel SEU hardened 10T PD SOI SRAM cell is proposed. By dividing each pull-up and pull-down transistor in the cross-coupled inverters into two cascaded transistors, this cell suppresses the parasitic BJT and source-drain penetration charge collection effect in PD SOI transistor which causes the SEU in PD SOI SRAM. Mixed-mode simulation shows that this novel cell completely solves the SEU, where the ion affects the single transistor. Through analysis of the upset mechanism of this novel cell, SEU performance is roughly equal to the multiple-cell upset performance of a normal 6T SOI SRAM and it is thought that the SEU performance is 17 times greater than traditional 6T SRAM in 45nm PD SOI technology node based on the tested data of the references. To achieve this, the new cell adds four transistors and has a 43.4% area overhead and performance penalty.