3D Vertical RRAM Research Articles

Graphene-based 3D XNOR-VRRAM with ternary precision for neuromorphic computing

Recent studies on neural network quantization have demonstrated a beneficial compromise between accuracy, computation rate, and architecture size. Implementing a 3D Vertical RRAM (VRRAM) array accompanied by device scaling may further improve such networks’ density and energy consumption. Individual device design, optimized interconnects, and careful material selection are key factors determining the overall computation performance. In this work, the impact of replacing conventional devices with microfabricated, graphene-based VRRAM is investigated for circuit and algorithmic levels. By exploiting a sub-nm thin 2D material, the VRRAM array demonstrates an improved read/write margins and read inaccuracy level for the weighted-sum procedure. Moreover, energy consumption is significantly reduced in array programming operations. Finally, an XNOR logic-inspired architecture designed to integrate 1-bit ternary precision synaptic weights into graphene-based VRRAM is introduced. Simulations on VRRAM with metal and graphene word-planes demonstrate 83.5 and 94.1% recognition accuracy, respectively, denoting the importance of material innovation in neuromorphic computing.

Layer‐dependent resistance variability assessment on 2048 8‐layer 3D vertical RRAMs

Non-filament 3D vertical RRAM (VRRAM) is a promising technology for emerging high-density memory applications. In this Letter, the layer-dependent resistance variability at both low resistance state (LRS) and high resistance state (HRS) is assessed on state-of-the-art 8-layer 3D VRRAMs. 2048 devices are measured with the aid of an FPGA-controlled relay matrix which enables automated switching of devices without changing the cabling. The results show LRS exhibits little layer dependence while both the average and the standard variation of HRS decrease from the top layer to the bottom layer. A qualitative speculation is proposed to explain the observation based on the high-resolution transmission electronic microscope image. This work is beneficial for future 3D VRRAM circuit design and performance improvement.

A vacancy-modulated self-selective resistive switching memory with pronounced nonlinear behavior

In this study, we report a self-selective (nonlinear) resistive switching memory cell, with high on-state half-bias nonlinearity of ~ 650, sub-μA operating current, and high On/Off ratios above 100×. Regarding the cell structure, a thermal oxidized HfO x layer in combination with a sputtered Ta2O5 layer was configured as an active stack, with Pt and Hf as top and bottom electrodes, respectively. The Ta2O5 acts as a selective layer as well as a series resistor, which could make the resistive switching happened in HfO x layer. Through the analysis of the physicochemical properties and electrical conduction mechanisms at each state, a vacancy-modulated resistance switching model was proposed to explain the switching behavior. The conductivity of HfO x layer was changed by polarity-dependent drift of the oxygen vacancy (V o), resulting in an electron hopping distance change during switching. With the help of Ta2O5 selective layer, high nonlinearity observed in low resistance state. The proposed material stack shows a promising prospect to act as a self-selective cell for 3D vertical RRAM application.

Tuning resistive switching parameters in Si3N4-based RRAM for three-dimensional vertical resistive memory applications

In this work, new 3D vertical RRAM device with silicon CMOS compatibility and the possible fabrication process are presented. RRAM devices based on Ni/Si3N4/p+-Si stack which are applicable in our proposed 3D vertical RRAM structure were fabricated in order to reveal the effects of switching layer thickness and compliant current on resistive switching parameters. Forming-less behavior can be easily achieved by controlling thickness of the Si3N4 layer. It is found that the high- and low-resistance state can be effectively modulated by the film thickness and compliance current, respectively.

Study of multi-level characteristics for 3D vertical resistive switching memory.

Three-dimensional (3D) integration and multi-level cell (MLC) are two attractive technologies to achieve ultra-high density for mass storage applications. In this work, a three-layer 3D vertical AlOδ/Ta2O5-x/TaOy resistive random access memories were fabricated and characterized. The vertical cells in three layers show good uniformity and high performance (e.g. >1000X HRS/LRS windows, >1010 endurance cycles, >104 s retention times at 125°C). Meanwhile, four level MLC is demonstrated with two operation strategies, current controlled scheme (CCS) and voltage controlled scheme (VCS). The switching mechanism of 3D vertical RRAM cells is studied based on temperature-dependent transport characteristics. Furthermore, the applicability of CCS and VCS in 3D vertical RRAM array is compared using resistor network circuit simulation.