3D Resistive Random Access Memory Research Articles

An Efficient 3D ReRAM Convolution Processor Design for Binarized Weight Networks

Convolutional neural networks (CNNs) have been evolving with tremendous success in visual recognition, obtaining human-level accuracy. The conventional hardware architecture, however, is facing difficulty in realizing real-time and energy-efficient operations on CNN. To efficiently operate CNN algorithms on the hardware, researchers are actively studying processing-in-memory (PIM) with resistive random-access memory (ReRAM). Digital PIM is particularly attractive because analog designs struggle with undesirable device properties and require additional circuits like analog-to-digital converter and digital-to-analog converter. However, the massive area originated from digital PIM is a hindrance to its applications. In this work, we present a three-dimensional (3D) ReRAM convolution logic processor design to tackle the limitation of digital PIM. At the hardware level, we leverage 3D ReRAM to take advantage of its area efficiency. The design simplicity without accuracy loss is accomplished by exploiting binarized weight networks (BWNs) at the algorithm level. Specifically, our 3D ReRAM processor computes the convolution of BWN based on a presumed full adder and a split-half addition scheme, which are proposed in this brief to maximize resource consumption efficiency. As a result, the proposed design achieves 3.7× to 5.7× and 5× to 42.5× area- and time-saving according to the bit precision in comparison to the original digital PIM.

Effect of Initial Synaptic State on Pattern Classification Accuracy of 3D Vertical Resistive Random Access Memory (VRRAM) Synapses

Amidst the considerable attention artificial intelligence (AI) has attracted in recent years, a neuromorphic chip that mimics the biological neuron has emerged as a promising technology. Memristor or Resistive random-access memory (RRAM) is widely used to implement a synaptic device. Recently, 3D vertical RRAM (VRRAM) has become a promising candidate to reducing resistive memory bit cost. This study investigates the operation principle of synapse in 3D VRRAM architecture. In these devices, the classification response current through a vertical pillar is set by applying a training algorithm to the memristors. The accuracy of neural networks with 3D VRRAM synapses was verified by using the HSPICE simulator to classify the alphabet in 7×7 character images. This simulation demonstrated that 3D VRRAMs are usable as synapses in a neural network system and that a 3D VRRAM synapse should be designed to consider the initial value of the memristor to prepare the training conditions for high classification accuracy. These results mean that a synaptic circuit using 3D VRRAM will become a key technology for implementing neural computing hardware.

Reduction of thermal disturbances in 3D 1S1R RRAM crossbar arrays for neuromorphic computing

Recently, analog behaviors in resistive random-access memory (RRAM) have been proposed as a promising circuit implementation for neuromorphic computing. However, to date, there have been relatively few studies on the issue of resistance degradation (computing weight) induced by thermal disturbances in high-density RRAM arrays. In this paper, thermal simulations of a three-dimensional (3D) one-selector, one-resistor (1S1R) RRAM crossbar array for neuromorphic computing were performed using the COMSOL Multiphysics software. Four factors influencing the thermal disturbance problem were considered: distances between adjacent devices, thermal conductivity of the insulating material, the resistance of the low-resistance state (LRS) of the RRAM, and the programming speed. Thermal disturbances were found to be more severe when the device spacing was less than 200 nm. Higher thermal conductivities of the insulating material, a larger LRS resistance, and a faster operational speed were found to effectively reduce the thermal disturbances in 3D 1S1R RRAM crossbar arrays. The use of sub-nanosecond pulses solved the thermal issues to the greatest extent.

Tubular 3D Resistive Random Access Memory Based on Rolled-Up h-BN Tube.

Due to their advantages compared with planar structures, rolled-up tubes have been applied in many fields, such as field-effect transistors, compact capacitors, inductors, and integrative sensors. On the other hand, because of its perfect insulating nature, ultrahigh mechanical strength and atomic thickness property, 2D hexagonal boron nitride (h-BN) is a very suitable material for rolled-up memory applications. In this work, a tubular 3D resistive random access memory (RRAM) device based on rolled-up h-BN tube is realized, which is achieved by self-rolled-up technology. The tubular RRAM device exhibits bipolar resistive switching behavior, nonvolatile data storage ability, and satisfactorily low programming current compared with other 2D material-based RRAM devices. Moreover, by releasing from the substrate, the footprint area of the tubular device is reduced by six times. This tubular RRAM device has great potential for increasing the data storage density, lowering the power consumption, and may be applied in the fields of rolled-up systems and sensing-storage integration.

(Invited) Graphene Plane Electrode for Low Power 3D Resistive Random Access Memory

In this work, we introduce one of the world’s thinnest non-volatile memory stacked in a 3-dimensional vertical structure. We exploit the edge of an atomically thin graphene layer and form a metal oxide resistive memory using HfOx as the switching oxide. We found that such thin memory has potential for highly integrated storage system with memory density higher than the same memory structure made using thin metal layer. We also confirm that it is not possible to build such thin memory with conventional metal because the sheet resistance of metal dramatically increases as it is thinned down to less than 5 nm.

(Invited) Graphene Plane Electrode for Low Power 3D Resistive Random Access Memory

The central theme of the “Internet of Things” is a societal and technological movement towards ubiquitous, abundant-data computing. Such transformation requires real-time analytics on enormous quantities of data collected by a vast network of sensors and other autonomous sources feeding into the data cloud. Current computing technology, however, cannot satisfy such applications with the required throughput and necessary energy efficiency. The next technology frontier will be monolithically integrated chips with 3-dimensionally interleaved memory and logic for unprecedented data bandwidth with reduced energy consumption. In this work, we exploit the atomically thin nature of the graphene plane to assemble a resistive memory stacked in a vertical 3D structure. Compared to the same architecture that uses conventional metal (Pt) as an RRAM electrode, the atomically thin graphene edge electrode was able to reduce power consumption by ×300 while producing a highly localized electrical field for oxygen anion migration. The switching energy of this device is one of the lowest reported compared to existing alternative memory technologies. Importantly, circuit analysis of the 3D architecture using experimentally measured device properties show higher storage potential for graphene devices compared that of metal based devices.

Thermal crosstalk in 3-dimensional RRAM crossbar array.

High density 3-dimensional (3D) crossbar resistive random access memory (RRAM) is one of the major focus of the new age technologies. To compete with the ultra-high density NAND and NOR memories, understanding of reliability mechanisms and scaling potential of 3D RRAM crossbar array is needed. Thermal crosstalk is one of the most critical effects that should be considered in 3D crossbar array application. The Joule heat generated inside the RRAM device will determine the switching behavior itself, and for dense memory arrays, the temperature surrounding may lead to a consequent resistance degradation of neighboring devices. In this work, thermal crosstalk effect and scaling potential under thermal effect in 3D RRAM crossbar array are systematically investigated. It is revealed that the reset process is dominated by transient thermal effect in 3D RRAM array. More importantly, thermal crosstalk phenomena could deteriorate device retention performance and even lead to data storage state failure from LRS (low resistance state) to HRS (high resistance state) of the disturbed RRAM cell. In addition, the resistance state degradation will be more serious with continuously scaling down the feature size. Possible methods for alleviating thermal crosstalk effect while further advancing the scaling potential are also provided and verified by numerical simulation.

Experimental study of plane electrode thickness scaling for 3D vertical resistive random access memory

The vertical scaling for the multi-layer stacked 3D vertical resistive random access memory (RRAM) cross-point array is investigated. The thickness of the multi-layer stack for a 3D RRAM is a key factor for determining the storage density. A vertical RRAM cell with plane electrode thickness (tm) scaled down to 5 nm, aiming to minimize 3D stack height, is experimentally demonstrated. An improvement factor of 5 in device density can be achieved as compared to a previous demonstration using a 22 nm thick plane electrode. It is projected that 37 layers can be stacked for a lithographic half-pitch (F) = 26 nm and total thickness of one stack (T) = 21 nm, delivering a bit density of 72.8 nm2/cell.

Structural, optical, electrical and resistive switching properties of ZnO thin films deposited by thermal and plasma-enhanced atomic layer deposition

In this study, we report on a systematical investigation on the crystal structure, optical and electrical properties of ZnO thin films grown by thermal and remote plasma-enhanced atomic layer deposition (Thermal ALD and PEALD) and their applications in resistive switching devices. The conductivity of ZnO films grown by Thermal ALD at 200°C is ∼169S/cm, demonstrating a good potential for the applications in transparent conducting films. It is possible to deposit ZnO films with good structural quality and few defects at lower temperatures by PEALD. The Al/PEALD-ZnO/Pt devices show good resistive switching properties, while the devices using Thermal ALD ZnO films failed to show any resistive switching behavior, but a perfect Ohmic behavior. The thickness ZnO active layer has a strong effect on the device properties. When the thickness of ZnO film is ∼23nm, the high state-resistance to low state-resistance ratio maintains at larger than 103, while the current compliance for safe operation is ∼1mA much smaller than those for devices with thick active layers. The results have demonstrated the PEALD grown ZnO films have the excellent properties for the applications in high-density 3D resistive random access memory.