3D Network-on-Chip Architectures Research Articles

Learning-Based Application-Agnostic 3D NoC Design for Heterogeneous Manycore Systems

The rising use of deep learning and other big-data algorithms has led to an increasing demand for hardware platforms that are computationally powerful, yet energy-efficient. Due to the amount of data parallelism in these algorithms, high-performance 3D manycore platforms that incorporate both CPUs and GPUs present a promising direction. However, as systems use heterogeneity (e.g., a combination of CPUs, GPUs, and accelerators) to improve performance and efficiency, it becomes more pertinent to address the distinct and likely conflicting communication requirements (e.g., CPU memory access latency or GPU network throughput) that arise from such heterogeneity. Unfortunately, it is difficult to quickly explore the hardware design space and choose appropriate tradeoffs between these heterogeneous requirements. To address these challenges, we propose the design of a 3D Network-on-Chip (NoC) for heterogeneous manycore platforms that considers the appropriate design objectives for a 3D heterogeneous system and explores various tradeoffs using an efficient ML-based multi-objective optimization technique. The proposed design space exploration considers the various requirements of its heterogeneous components and generates a set of 3D NoC architectures that efficiently trades off these design objectives. Our findings show that by jointly considering these requirements (latency, throughput, temperature, and energy), we can achieve 9.6% better Energy-Delay Product on average at nearly iso-temperature conditions when compared to a thermally-optimized design for 3D heterogeneous NoCs. More importantly, our results suggest that our 3D NoCs optimized for a few applications can be generalized for unknown applications as well. Our results show that these generalized 3D NoCs only incur a 1.8% (36-tile system) and 1.1% (64-tile system) average performance loss compared to application-specific NoCs.

Extending BookSim2.0 and HotSpot6.0 for power, performance and thermal evaluation of 3D NoC architectures

With the increase in number and complexity of cores and components in Chip-Multiprocessors (CMP) and Systems-on-Chip (SoCs), a highly structured and efficient on-chip communication network is required to achieve high-performance and scalability. Network-on-Chip (NoC) has emerged as a reliable communication framework in CMPs and SoCs. Many 2-D NoC architectures have been proposed for efficient on-chip communication. Cycle accurate simulators model the functionality and behaviour of NoCs by considering micro-architectural parameters of the underlying components to estimate performance, power and energy characteristics. Employing NoCs in three-dimensional integrated circuits (3D-ICs) can further improve performance, energy efficiency, and scalability characteristics of 3D SoCs and CMPs. Minimal error estimation of energy and performance of NoC components is crucial in architecture trade-off studies. Accurate modeling of re:Horizontal and vertical links by considering micro-architectural and physical characteristics reduces the error in power and performance estimation of 3D NoCs. Additionally, mapping the temperature distribution in a 3D NoC reduces estimation error.This paper presents the 3D NoC modelling capabilities extended in two existing state-of-the-art simulators, viz., the 2D NoC Simulator - BookSim2.0 and the thermal behaviour simulator - HotSpot6.0. With the extended 3D NoC modules, the simulators can be used for power, performance and thermal measurements through micro-architectural and physical parameters. The major extensions incorporated in BookSim2.0 are: Through Silicon Via power and performance models, 3D topology construction modules, 3D Mesh topology construction using variable X, Y, Z radix, tailored routing modules for 3D NoCs. The major extensions incorporated in HotSpot6.0 are: parameterized 2D router floorplan, 3D router floorplan including Through Silicon Vias (TSVs), power and thermal distribution models of 2D and 3D routers.Using the extended 3D modules, performance (average network latency), and energy efficiency metrics (Energy-Delay Product) of variants of 3D Mesh and 3D Butterfly Fat Tree topologies have been evaluated using synthetic traffic patterns. Results show that the 4-layer 3D Mesh is 2.2 × better than 2-layer 3D Mesh and 4.5 × better than 3D BFT variants in terms of network latency. 3D Mesh variants have the lowest Energy Delay Product (EDP) compared to 3D BFT variants as there is an 80% reduction in link lengths and up to 3 × more TSVs. Another observation is that the EDP of the 4-layer 3D BFT (with transpose traffic) is 1.5 × the EDP of the 4-layer 3D Mesh (with transpose traffic). Further optimizations towards a tailored 3D BFT for transpose traffic could reduce this EDP gap with the 4-layer 3D Mesh. From the 3D NoC heat maps, it was found that the edge routers in the floorplan of the tested 3D Mesh and 3D BFT topologies have the least ambient temperature.

An Efficient Partitioning Algorithm Based on Hypergraph for 3D Network-On-Chip Architecture Floorplanning

Network-on-Chip (NoC) supplies a scalable and fast interconnect for the communication between the different IP cores in the System-on-Chip (SoC). With the growing complexity in consumer embedded systems, the emerging SoC architectures integrate more and more components for the different signal processing tasks. Two dimensional Network-on-Chip (2D NoC) becomes a bottleneck for the development of the SoC architecture because of its limitation on the area of chip and the long latency. In this case, SoC research is forcing on the exploration of three dimensions (3D) technology for developing the next generation of large SoC which integrates three dimensional Network-on-Chip (3D NoC) for the communication architecture. 3D design technology resolves the vertical inter-layer connection issue by Through-Silicon Vias (TSVs). However, TSVs occupy significant silicon area which limits the inter-layer links of the 3D NoC. Therefore, the task partitioning on 3D NoC must be judicious in large SoC design. In this paper, we propose an efficient layer-aware partitioning algorithm based on hypergraph (named ELAP-NoC) for the task partitioning with TSV minimization for 3D NoC architecture floorplanning. ELAP-NoC contains divergence stage and convergence stage. ELAP-NoC supplies firstly a multi-way min-cut partitioning to gradually divide a given design layer by layer in the divergence stage in order to get an initial solution, then this solution is refined in convergence stage. The experiments show that ELAP-NoC performs a better capacity in the partitioning of the different numbers of cores which supplies the first step for the 3D NoC floorplanning.

Reliability- and performance-driven mapping for regular 3D NoCs using a novel latency model and Simulated Allocation

Network-on-Chip (NoC) -based communication architecture is promising in addressing the communication bottlenecks in current and future multicore processors. In this work, we consider the application-specific mapping problem and electromigration (EM) -induced through-silicon via (TSV) reliability issue in tile-based three-dimension (3D) NoC architectures. In 3D NoCs, network contention may result in unacceptable communication delay among the processing cores and thus has significant effect on the system performance. So we propose a new latency model for the routers which characterizes the network contentions among different traffic flows from sharing of network resources. Then we solve the core mapping problem by a fast while efficient stochastic algorithm called Simulated Allocation (SAL), which integrates our new latency model and also aims to optimize the communication power, latency in the mapping procedure. After that, we use an incremental method to optimize the reliability of the TSVs. Experimental results show that, contention-aware model (CAM) has 25% larger network latency than our latency model; compared with particle swarm optimization (PSO), our SAL algorithm can achieve 7% less power with about 7.5 × run-time speedup; as for reliability, our method can achieve better results (up to 10 × increase in terms of the void nucleation time (VNT)) with 7.64% increased latency.

Analyzing power-thermal-performance trade-offs in a high-performance 3D NoC architecture

The emergence of three-dimensional (3D) network-on-chip (NoC) has revolutionized the design of high-performance and energy efficient manycore chips. However, in general, 3D NoC architectures still suffer from high power density and the resultant thermal hotspots leading to functionality and reliability concerns over time. The power consumption and thermal profiles of 3D NoCs can be improved by incorporating a Voltage Frequency Island (VFI)-based power management strategy and Reciprocal Design Symmetry (RDS)-based floor planning. In this paper, we undertake a detailed design space exploration for 3D NoC by considering power-thermal-performance (PTP) trade-offs. We specifically consider a small-world network-enabled 3D NoC (3D SWNoC) in this performance evaluation due to its superior performance and energy-efficiency compared to any other existing 3D NoC architectures. We demonstrate that the VFI-enabled 3D SWNoC lowers the energy-delay-product (EDP) by 57.3% on an average compared to a 2D MESH without VFI. Moreover, by incorporating VFI, we reduce the maximum temperature of 3D SWNoC by 15.2% on an average compared to the non-VFI counterpart. By complementing the VFI-based power management with RDS-based floor planning, the 3D SWNoC reduces the maximum temperature by 25.1% on an average compared to the non-VFI counterpart.

HRC: A 3D NoC Architecture with Genuine Support for Runtime Thermal-Aware Task Management

In spite of escalating thermal challenges imposed by high power consumption, most reported 3D Network-on-chip (NoC) systems that adopt classic 3D cube (mesh) topology are unable to tackle the thermal management issues directly at the architectural level. Rather, to avoid chip being overheated, tasks running in a “hot” node have to be migrated to a “cooler” one, resulting in increased distance between communicating nodes and ultimately poor performance. In this paper, we propose a new 3D NoC architecture that genuinely supports runtime thermal-aware task management. Dubbed Hierarchical Ring Cluster (HRC), this new hierarchical 3D NoC architecture has three levels across its entire network hierarchy: 1) nodes are grouped as rings, 2) rings are then grouped into cubes, and 3) multiple cubes are connected to form the whole network. Routing in a HRC system is also performed in a hierarchical manner: Paths are set up within rings using low latency circuit switching, and data that need to cross the rings or cubes are routed following dimension-order routing supported by wormhole switching. In this organization, “hot” tasks that need to migrate can move along the rings without incurring increased communication distances. Our experimental results have confirmed that the proposed HRC architecture has a much lower network latency than other known 3D NoC architectures. When working with runtime thermal-aware task migration approaches, HRC can help reduce latency by as much as 80 percent compared to thermal-aware task migration approaches applied to 3D mesh NoC topologies.

Dynamically reconfigurable simulation platform for 3D NoC based on multi-FPGA

Taking advantage of Three Dimension (3D) Integrated Circuit (IC) technology, 3D Network-on-Chip (NoC) is becoming a promising architecture of high-performance System-on-Chip (SoC). To model 3D NoC and to evaluate the performance fast and accurately, the simulation method is therefore critical issue. Compared to software simulation, Field Programmable Gate Array (FPGA) based simulation can offer a high speed validation process with a higher accuracy. But there still exist some difficulties such as partition, scalability and so on. This paper proposed a novel multi-FPGA simulation platform, RcEF3Ns (Reconfigurable Simulation on multi-FPGA for 3D NoCs), based on Xilinx Virtex-6 FPGAs. The design method of RcEF3Ns employs a single FPGA to manage vertical transaction independently, supporting bus and network communication mechanism. All the parameters can be dynamically reconfigured on-chip to model 3D NoC architecture without re-synthesizing. The experiments show RcEF3Ns’ speedups over 10 times without sacrificing accuracy when compared to other hardware based platform.

Estimation of Optimized Energy and Latency Constraint for Task Allocation in 3d Network on Chip

In Network on Chip (NoC) rooted system, energy consumption is affected by task scheduling and allocation schemes which affect the performance of the system. In this paper we test the pre-existing proposed algorithms and introduced a new energy skilled algorithm for 3D NoC architecture. An efficient dynamic and cluster approaches are proposed along with the optimization using bio-inspired algorithm. The proposed algorithm has been implemented and evaluated on randomly generated benchmark and real life application such as MMS, Telecom and VOPD. The algorithm has also been tested with the E3S benchmark and has been compared with the existing mapping algorithm spiral and crinkle and has shown better reduction in the communication energy consumption and shows improvement in the performance of the system. On performing experimental analysis of proposed algorithm results shows that average reduction in energy consumption is 49%, reduction in communication cost is 48% and average latency is 34%. Cluster based approach is mapped onto NoC using Dynamic Diagonal Mapping (DDMap), Crinkle and Spiral algorithms and found DDmap provides improved result. On analysis and comparison of mapping of cluster using DDmap approach the average energy reduction is 14% and 9% with crinkle and spiral.

Energy reduction in 3D NoCs through communication optimization

Network-on-Chip (NoC) architectures and three-dimensional (3D) integrated circuits have been introduced as attractive options for overcoming the barriers in interconnect scaling while increasing the number of cores. Combining these two approaches is expected to yield better performance and higher scalability. This paper explores the possibility of combining these two techniques in a heterogeneity aware fashion. Specifically, on a heterogeneous 3D NoC architecture, we explore how different types of processors can be optimally placed to minimize data access costs. Moreover, we select the optimal set of links with optimal voltage levels. The experimental results indicate significant savings in energy consumption across a wide range of values of our major simulation parameters.

Performance and cost metrics analysis of a 3D NoC topology using network calculus

The packet switching based Network-on-Chip (NoC) is an obvious interconnect design alternative to the shared bus, crossbar or ring based on-chip communication architecture used in System-on-Chips (SoCs). The advent of the three dimensional NoC (3D NoC) architecture attracts added interest as it offers improved performance and shorter global interconnect. In the 3D NoC architecture, topology plays a vital role in determining the performance of the interconnect architecture. The performance and cost metrics of the 3D NoC topology are evaluated by using simulation in general. However, analytical models provide more insights on how the traffic related parameters influence the performance of the topology. In this paper, the traffic related parameters of a 3D NoC topology, namely 3D Recursive Network Topology (3D RNT) are evaluated by using network calculus based methodology and the results of the evaluation are compared against the results produced using simulation.

Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation

The Network-on-Chip (NoC) paradigm has emerged as a revolutionary methodology for integrating a very high number of intellectual property (IP) blocks in a single die. The achievable performance benefit arising out of adopting NoCs is constrained by the performance limitation imposed by the metal wire, which is the physical realization of communication channels. With technology scaling, only depending on the material innovation will extend the lifetime of conventional interconnect systems a few technology generations. According to International Technology Roadmap for Semiconductors (ITRS) for the longer term, new interconnect paradigms are in need. The conventional two dimensional (2D) integrated circuit (IC) has limited floor-planning choices, and consequently it limits the performance enhancements arising out of NoC architectures. Three dimensional (3D) ICs are capable of achieving better performance, functionality, and packaging density compared to more traditional planar ICs. On the other hand, NoC is an enabling solution for integrating large numbers of embedded cores in a single die. 3D NoC architectures combine the benefits of these two new domains to offer an unprecedented performance gain. In this paper we evaluate the performance of 3D NoC architectures and demonstrate their superior functionality in terms of throughput, latency, energy dissipation and wiring area overhead compared to traditional 2D implementations.