3D NAND Flash Memory Research Articles

Analysis of cell characteristics using back oxide trap charge effect in various channel structures of 3D-NAND flash

Abstract This study investigates how trap charges in the back oxide layer affect the memory performance of 3D NAND flash memory. We used TCAD to simulate the effect on cell reliability, focusing on retention and interference characteristics, based on changes in current paths and program speed as initial cell characteristics. Additionally, we applied these findings to various channel structures — planar, concave, and convex — that can occur in 3D NAND. Our results indicate that the optimal trap charge for enhancing cell performance lies between -10¹¹ and -10¹⁰ /cm³ and should not exceed -1011 /cm3. Through this research, we can expect the potential for effectively inserting trap charges in actual manufacturing processes to improve the performance characteristics of 3D NAND cells.

HAIPO: Hybrid AI Algorithm-Based Post-Fabrication Optimization for Modern 3D NAND Flash Memory

To successfully meet the various requirements of modern storage systems, NAND flash memory should be highly optimized by precisely tuning a huge number of internal operating parameters. Although 3D NAND flash memory succeeds in increasing the capacity of storage systems, its complex architecture and unique error behavior make such optimization a more difficult and time-consuming process during NAND manufacturing. In this paper, we introduce HAIPO, a novel methodology for post-fabrication optimization of NAND flash memory, which is an essential step in the manufacturing process of modern 3D NAND flash memory to simultaneously meet various requirements on reliability, performance, yield, etc. HAIPO is based on simple machine-learning approaches that consist of (i) a lightweight deep-learning (DL) model to generate initial device parameters and (ii) an evolutionary algorithm (EA) to explore device parameters automatically. To more effectively explore device parameters, we introduce three key guidelines for each generation in the EA: (1) domain-specific rules, (2) recent optimization results, and (3) online Bayesian simulation, respectively, to enable quick optimization for a huge number of device parameters within the limited product turnaround time (TAT). In addition, we integrate two optimization modules with HAIPO to improve optimization efficiency even in environments with severe process variation. We demonstrate the feasibility and effectiveness of HAIPO using real 320 3D TLC/QLC NAND flash chips, showing significant performance and reliability improvements by up to 8.8% and 12% on average, respectively, within a quite limited optimization TAT.

Investigation of on-pitch SGD structure induced Vth distribution tails downshift in 3D NAND flash memory

Investigation of on-pitch SGD structure induced Vth distribution tails downshift in 3D NAND flash memory

Low-temperature etching of silicon oxide and silicon nitride with hydrogen fluoride

Etching of high aspect ratio features into alternating SiO2 and SiN layers is an enabling technology for the manufacturing of 3D NAND flash memories. In this paper, we study a low-temperature or cryo plasma etch process, which utilizes HF gas together with other gas additives. Compared with a low-temperature process that uses separate fluorine and hydrogen gases, the etching rate of the SiO2/SiN stack doubles. Both materials etch faster with this so-called second generation cryo etch process. Pure HF plasma enhances the SiN etching rate, while SiO2 requires an additional fluorine source such as PF3 to etch meaningfully. The insertion of H2O plasma steps into the second generation cryo etch process boosts the SiN etching rate by a factor of 2.4, while SiO2 etches only 1.3 times faster. We observe a rate enhancing effect of H2O coadsorption in thermal etching experiments of SiN with HF. Ammonium fluorosilicate (AFS) plays a salient role in etching of SiN with HF with and without plasma. AFS appears weakened in the presence of H2O. Density functional theory calculations confirm the reduction of the bonding energy when NH4F in AFS is replaced by H2O.

Advanced spectroscopic methods for probing in-gap defect states in amorphous SiNx for charge trap memory applications

Silicon nitride (SiNx) serves as the charge trap layer in current 3D NAND flash memory devices. The precise formation mechanism and electronic structure of localized defect trap states in SiNx remain elusive. Here, we present a refined experimental methodology to elucidate the in-gap defect states and the band gaps in amorphous SiNx thin films. Our approach integrates high-resolution reflection electron energy loss spectroscopy (REELS) and spectroscopic ellipsometry (SE) for comprehensive analysis. By systematical analysis, we aim to provide a robust method for determining in-gap electronic states in SiNx. We investigated two different SiNx films prepared by plasma-enhanced chemical vapor deposition and sputtering. Our analysis revealed several distinct in-gap states and determined band gap energies. This approach not only provide advanced spectroscopic methods to characterize the defect electronic states in SiNx, but also applicable to other large band gap semiconductors or dielectrics to predict device-level characteristics for future devices.

A machine learning framework for predictive electron density modelling to enhance 3D NAND flash memory performance

Data storage in electronic devices has been revolutionised by 3D NAND flash memory. However, polycrystalline silicon and grain boundaries offer issues that greatly affect memory performance in terms of string current and Program-Erase Threshold Voltage window (Vt –Window). Scientists need to learn more about how grain size, channel thickness, and trap density affect electron behaviour to improve the efficiency of memory chips. Regression models are used in this work to forecast fluctuations in electron density along the channel in 3D NAND string devices. The dataset, which was derived using TCAD simulations, has a sizable number of samples that show the electron density as a function of channel length. We assess their performance using R2 scores and RMSE values using regression models such as Linear Regression, Random Forest, K-Neighbour Regressor, Decision Tree, Gradient Boosting, XGBRegressor, CatBoosting Regressor, and AdaBoost Regressor. By improving our knowledge of how electrons behave in transistor channels, this work contributes to the optimisation of 3D NAND flash memory.

High-density 3D-NAND flash with dual-string select line (D-SSL)

In this study, high-density 3D-NAND flash memory is proposed. Using D-SSL, lateral shrink of cell area can be achieved by distinguishing two strings in a word-line (WL). We verify erase/program and read characteristics using technology computer-aided design (TCAD) simulations with rigorous calibrated condition. The proposed high density NAND flash has normally-on state SSLs through additional process and electrical treatment. In the conventional reference NAND flash, the cell string connected to the bit-line (BL) is distinguished by WL cut (WLC). On the other hand, in the proposed high density NAND flash, the cell string is selected by utilizing the normally-on state SSLs using trapped hole and doped arsenic at the intersection of SSL1 and SSL2. Compared with the conventional scheme, the proposed D-SSL exhibits almost same erase/program and read characteristics. Consequently, the proposed D-SSL scheme can increase memory density with reduced number of WLCs by distinguishing strings using D-SSL.

Innovative Programming Approaches to Address Z-Interference in High-Density 3D NAND Flash Memory

Increasing the bit density in 3D NAND flash memory involves reducing the pitch of ON (Oxide-Nitride) molds in the Z-direction. However, this reduction drastically increases Z-interference, adversely affecting cell distribution and accelerating degradation of reliability limits. Previous studies have shown that programming from the top word line (WL) to the bottom WL, instead of the traditional bottom-to-top approach, alleviates Z-interference. Nevertheless, detailed analysis of how Z-interference varies at each WL depending on the programming sequence remains insufficient. This paper investigates the causes of Z-interference variations at Top, Middle, and Bottom WLs through TCAD analysis. It was found that as more electrons are programmed into WLs within the string, Z-interference variations increase due to increased resistance in the poly-Si channel. These variations are exacerbated by tapered vertical channel profiles resulting from high aspect ratio etching. To address these issues, a method is proposed to adjust bitline biases during verification operations of each WL. This method has been validated to enhance the performance and reliability of 3D NAND flash memory.

Systematic Analysis of Spacer and Gate Length Scaling on Memory Characteristics in 3D NAND Flash Memory

This study investigates the impact of oxide/nitride (ON) pitch scaling on the memory performance of 3D NAND flash memory. We aim to enhance 3D NAND flash memory by systematically reducing the spacer length (Ls) and gate length (Lg) to achieve improved memory characteristics. Using TCAD simulations, we evaluate the effects of Ls and Lg scaling on the program speed, erase speed, and Z-interference. Furthermore, we examine the influence of concave and convex channel structures in the context of Ls and Lg scaling. By analyzing the distributions of electron and hole-trapped charges, we provide insights into optimizing the trade-offs between the memory window and retention characteristics. This research offers valuable guidelines for improving the reliability and performance of 3D NAND flash memory through a systematic analysis of spacer and gate length scaling.

Low‐Power Charge Trap Flash Memory with MoS2 Channel for High‐Density In‐Memory Computing

AbstractWith the rise of on‐device artificial intelligence (AI) technology, the demand for in‐memory comptuing has surged for data‐intensive tasks on edge devices. However, on‐device AI requires high‐density, low‐power memory‐based computing to efficiently handle large data volumes. Here, this study proposes a reliable multilevel, high gate‐coupling ratio memory device with MoS2 channel tailored for high‐density 3D NAND Flash‐based in‐memory computing. The MoS2 channel, featured by its small bandgap and high‐mobility, facilitates reliable memory window of approximately 8 V thanks to erase operation through hole injection. This not only suppresses vertical charge loss but also alleviates the burden on voltage generator circuits, indicating the suitability of MoS2 as channel material for 3D NAND Flash architecture. Additionally, a low‐k (≈2.2) tunneling layer deposited via initiated chemical vapor deposition increases the gate‐coupling ratio, thereby reducing the operating voltage. Utilizing Au nanoparticles as the charge storage layer, MoS2 memory devices show synaptic plasticity with 6‐bit, endurance (104 cycles), read disturbance (105 cycles), and retention times (105 s). Furthermore, device‐to‐system simulations for neural networks based on MoS2‐memory devices have successfully achieved a fingerprint recognition of 95.8%. These results provide the foundation to develop multi‐bit MoS2‐memory devices for AI accelerators and 3D NAND Flash memory.

DMMC: A Polar Code Construction Method for Improving Performance in TLC NAND Flash

3D TLC NAND flash memory significantly increases the storage capacity but makes data more prone to errors. To address the reliability problem, Polar Code is one coding method that can reach the channel capacity1. However, the 3D NAND flash memory channel is uncertain due to the variation of retention time and program/erase(P/E) cycle. So it is difficult to construct Polar Code in NAND flash memory. This paper proposes a new Polar Code construction method called Dynamic Merge Monte Carlo(DMMC). DMMC uses the Monte Carlo method to obtain the optimal Polar Code construction and then reduces the space overhead by combining similar construction so that it can be used in flash memory systems. Compared with the conventional method, the uncorrectable bit error rate(UBER) of the proposed method can reduce by up to 90.5%, and the read latency can reduce by more than 50%.

Characterizing and Optimizing LDPC Performance on 3D NAND Flash Memories

With the development of NAND flash memories’ bit density and stacking technologies, while storage capacity keeps increasing, the issue of reliability becomes increasingly prominent. Low-density parity check (LDPC) code, as a robust error-correcting code, is extensively employed in flash memory. However, when the RBER is prohibitively high, LDPC decoding would introduce long latency. To study how LDPC performs on the latest 3D NAND flash memory, we conduct a comprehensive analysis of LDPC decoding performance using both the theoretically derived threshold voltage distribution model obtained through modeling (Modeling-based method) and the actual voltage distribution collected from on-chip data through testing (Ideal case). Based on LDPC decoding results under various interference conditions, we summarize four findings that can help us gain a better understanding of the characteristics of LDPC decoding in 3D NAND flash memory. Following our characterization, we identify the differences in LDPC decoding performance between the Modeling-based method and the Ideal case. Due to the accuracy of initial probability information, the threshold voltage distribution derived through modeling deviates by certain degrees from the actual threshold voltage distribution. This leads to a performance gap between using the threshold voltage distribution derived from the Modeling-based method and the actual distribution. By observing the abnormal behaviors in the decoding with the Modeling-based method, we introduce an Offsetted Read Voltage ( Δ RV) method, for optimizing LDPC decoding performance by offsetting the reading voltage in each layer of a flash block. The evaluation results show that our Δ RV method enhances the decoding performance of LDPC on the Modeling-based method by reducing the total number of sensing levels needed for LDPC decoding by 0.67% to 18.92% for different interference conditions on average, under the P/E cycles from 3000 to 7000.

Channel Potential of Bandgap-Engineered Tunneling Oxide (BE-TOX) in Inhibited 3D NAND Flash Memory Strings

In this study, the channel potential of inhibited strings in 3D NAND flash memory using a bandgap-engineered tunneling oxide (BE-TOX) structure is analyzed. The equivalent oxide thickness (EOT) of the structure using BE-TOX was designed to be the same as the conventional 3D NAND flash memory, and the channel potentials of the down coupling phenomenon (DCP) and natural local self-boosting (NLSB) effect were analyzed. As a result, the BE-TOX structure was confirmed to have a higher channel potential in the DCP and NLSB than the conventional structure, making it relatively effective for program disturbance. The main reason for the difference in the channel potential between the BE-TOX and conventional structures is that adjacent cells have different threshold voltages (Vth). When the same program voltage (VPGM) and program time (TPGM) were applied during the program operation, Vth decreased in the BE-TOX structure, which increased the channel potential when DCP and NLSB occurred. Finally, a simulation was conducted by varying the thicknesses of the oxide and nitride in the BE-TOX structure. Despite the EOT being fixed and the thicknesses of both nitride and oxide being varied, the channel potential was affected.

Modeling Retention Errors of 3D NAND Flash for Optimizing Data Placement

Considering 3D NAND flash has a new property of process variation (PV) , which causes different raw bit error rates (RBER) among different layers of the flash block. This paper builds a mathematical model for estimating the retention errors of flash cells, by considering the factor of layer-to-layer PV in 3D NAND flash memory, as well as the factors of program/erase (P/E) cycle and retention time of data. Then, it proposes classifying the layers of flash block in 3D NAND flash memory into profitable and unprofitable categories, according to the error correction overhead. After understanding the retention error variation of different layers in 3D NAND flash, we design a mechanism of data placement, which maps the write data onto a suitable layer of flash block, according to the data hotness and the error correction overhead of layers, to boost read performance of 3D NAND flash. The experimental results demonstrate that our proposed retention error estimation model can yield a R 2 value of 0.966 on average, verifying the accuracy of the model. Based on the estimated retention error rates of layers, the proposed data placement mechanism can noticeably reduce the read latency by 29.8 % on average, compared with state-of-the-art methods against retention errors for 3D NAND flash memory.

Neural Network-Based prediction for Cross-Temperature induced VT distribution shift in 3D NAND flash memory

In this study, a neural network (NN) was proposed for predicting the VT characteristics of NAND flash memories under cross-temperature conditions. The training data were obtained from commercial NAND flash memory chip measurements at various temperatures. The VT distribution shift caused by cross-temperature was accurately predicted by investigating the optimum data dimensions while minimizing the data generation process. Two types of NNs were used to achieve an accurate VT distribution prediction, and each network was optimized using specific parameters based on the data characteristics at various program verify levels. Finally, quantitative and visual evaluations were conducted to verify the performance of the trained NNs. When the program-measured temperature varied from low to high, the NNs achieved mean errors of 1.87%, 1.41% at low and 0.34%, 0.77% at high for the average and width of the VT distribution, respectively. Similarly, when the temperature varied from high to low, the corresponding mean errors were 2.01%, 0.74% at high and 0.23%, 1.59% at low. These findings demonstrate that NNs can minimize the procedures for detecting the VT distribution shift caused by cross-temperature, thereby offering a promising approach to enhance reliability in the presence of such effects.

Analysis of Mechanical Stress on Fowler-Nordheim Tunneling for Program Operation in 3D NAND Flash Memory

This study investigated the relationship between mechanical stress and program efficiency in three-dimensional (3D) NAND flash memory devices. A stacked memory array transistor (SMArT) 3D NAND flash structure was modeled using a technology computer-aided design (TCAD) simulation. The mechanical stress distribution in the device depended on the deposition temperature (TD) of the constituent material. In particular, the TD of tungsten (TD,W) dominated the mechanical stress. The tensile stress on the polycrystalline silicon (poly-Si) channel increased as the TD,W decreased, and the compressive stress on the tunneling oxide (Tox) decreased. Consequently, the barrier height between Tox and poly-Si, and the effective electron mass decreased as the electric field in the Tox increased. These changes significantly increased the Fowler-Nordheim (FN) tunneling process and program efficiency, indicating the crucial performance of 3D NAND flash. Moreover, the mechanical stress caused by the differences in TD,W improved the program efficiency at a lower program voltage (VPGM). Therefore, a change in the mechanical stress based on decreasing TD,W improved the program efficiency through a higher FN tunneling process.

Smart Electrical Screening Methodology for Channel Hole Defects of 3D Vertical NAND (VNAND) Flash Memory

In order to successfully achieve mass production in NAND flash memory, a novel test procedure has been proposed to electrically detect and screen the channel hole defects, such as Not-Open, Bowing, and Bending, which are unique in high-density 3D NAND flash memory. Since channel hole defects lead to catastrophic failure (i.e., malfunction of basic NAND operations), detecting and screening defects in advance is one of the key challenges of guaranteeing the quality of flash products in the NAND manufacturing process. Based on analysis of the physical and electrical mechanisms of the channel hole defect, we have developed a two-step test procedure that consists of pattern-based and stress-based screen methodologies. By optimizing test patterns depending on the type of defect, the pattern-based screen is effective for detecting the type of Hard channel hole defects. The stress-based screen is carefully implemented to detect hidden Soft channel hole defects without degrading the reliability of NAND flash memory. In addition, we have attempted to further optimize the current version of our technique to minimize test time overhead, thus enabling 72.2% improvement in total test time. Experimental results using real 160 3D NAND flash chips show that our technique can efficiently detect and screen out various types of channel hole defects with minimum test time and negligible degradation in the flash reliability.

Improvement of warpage and leakage for 3D NAND flash memory

GLS (Gate line split) filling is a very important process in 3D NAND flash memory (3D NAND) fabrication. Filling materials in the GLS should have threefold properties, such as warpage tunability, leakage-free and low resistance. In this paper, the effects of different GLS filling materials (SiO2, W, amorphous silicon: A-Si) on F-attack, warpage and resistance were studied. GLS filled with A-Si shows best performance on warpage and F-attack. For 3D NAND, the number of stacked layers is predicted as a function of the wafer warpage, and the wafer warpage difference between GLS filled with A-Si and W was compared. With the same number of stacking layers, the wafer warpage post GLS filled with A-Si is smaller than that filled with W. Meanwhile, A-Si is produced by the decomposition of SiH4 by low pressure chemical vapor deposition (LPCVD) process, F-related by-product in the GLS filling material and consequent ACS (array common source) to WL (Word line) leakage by F-attack are avoided. A-Si is the best choice for GLS filling. This work provides an efficient method to solve the warpage and leakage problem in 3D NAND flash memory fabrication.

Optimizing Confined Nitride Trap Layers for Improved Z-Interference in 3D NAND Flash Memory

This paper presents an innovative approach to alleviate Z-interference in 3D NAND flash memory by proposing an optimized confined nitride trap layer structure. Z-interference poses a significant challenge in 3D NAND flash memory, especially with the reduction in cell spacing to accommodate an increased number of vertically stacked 3D NAND flash memories. While the confined nitride trap layer device designed for complete isolation of the trapping layer in three dimensions effectively reduces Z-interference, the results showed substantial variations based on the confined structure. To clarify this issue, we compared three distinct confined nitride trap layer structures and investigated their impact on Z-interference. Our findings indicate that the rectangle structure exhibited the most significant mitigation, implying that differences in the electric field applied to the poly silicon channel, which is influenced by the structure, and the increase in effective channel length are effective strategies for alleviating Z-interference. The proposed structure undergoes a comprehensive examination through technology computer-aided design (TCAD) simulations. Additionally, we introduce a practical process flow designed to minimize Z-interference.

An Optimized Device Structure with a Highly Stable Process Using Ferroelectric Memory in 3D NAND Flash Memory Applications

In this paper, we propose an optimized device structure with a highly stable process that addresses threshold voltage shift issues in the String-Select-Line (SSL) and Ground-Select-Line (GSL) gates using ferroelectric memory in 3D NAND flash memory applications. The proposed device utilizes nickel (Ni) instead of tungsten (W) for the GSL and SSL gates, enabling optimized polarization properties during the annealing process and leveraging the disparity in thermal expansion coefficients. Notably, the difference in thermal expansion coefficient from tungsten (W), employed in other Word Line (WL) gates, allows effective control over polarization properties. To validate the proposed structure, we fabricated and measured a Metal–Ferroelectric–Insulator–Silicon (MFIS) capacitor utilizing Hafnium–Zirconium Oxide (HZO) material. The measurement results indicate that a change in the upper metal layer results in a more than fivefold increase in the variance of polarization characteristics between the WL gates (responsible for the memory function) and the SSL and GSL gates dedicated to channel control. In addition, process simulation was conducted using the same device structure, confirming the application of tensile stress to the HZO thin film in the case of a W electrode and compressive stress in the case of a Ni electrode. Furthermore, applying this controlled polarization characteristic parameter to the 3D NAND flash memory structure revealed a reduction in the threshold voltage shift of the control gate from a previous change of 2.6 V or more to 0.05 V, facilitating stable control.