3D Field Programmable Gate Arrays Research Articles

Design and Optimization of a Horizontally Partitioned, High-Speed, 3D Tree-Based FPGA

The authors explore and design the traditional field-programmable gate array (FPGA) interconnect topologies and architectures that can play an important role in improving performance and density. The main architectures under exploration are tree-based and island-style Manhattan Mesh. Mesh-based design is the most common industrial and academic architecture. Numerous research and industrial designs have been developed to improve mesh-based FPGAs' performance, area, and power consumption. Nonetheless, when looking at performance metrics such as speed, area, and power, the gap is generally very wide for FPGAs compared to application-specific integrated circuits (ASICs). Despite their good properties, such as high logic density and area advantage, tree-based architectures have been overlooked up to now. This article addresses long wire length issues associated with tree-based programmable interconnects using 3D design and manufacturing technologies. Using their dedicated 3D design and optimization methodology, the authors show that 3D tree-based architecture is 1.5 times faster than the mesh-based counterpart.

Review of advanced FPGA architectures and technologies

Field Programmable Gate Array (FPGA) is an efficient reconfigurable integrated circuit platform and has become a core signal processing microchip device of digital systems over the last decade. With the rapid development of semiconductor technology, the performance and system integration of FPGA devices have been significantly progressed, and at the same time new challenges arise. The design of FPGA architecture is required to evolve to meet these challenges, while also taking advantage of ever increased microchip density. This survey reviews the recent development of advanced FPGA architectures, including improvement of the programming technologies, logic blocks, interconnects, and embedded resources. Moreover, some important emerging design issues of FPGA architectures, such as novel memory based FPGAs and 3D FPGAs, are also presented to provide an outlook for future FPGA development.

Interlaced switch boxes placement for three‐dimensional FPGA architecture design

SUMMARYThree‐dimensional (3D) field programmable gate array (FPGA) has evoked significant interest in wire‐length reduction for routing requirement. However, the complex design of the 3D switch boxes will limit the performance improvement and suffer from the area efficiency problems. This paper proposed a systematic graph model (SGM) for 3D switch boxes design to simplify the design process and reduce the storage memory for path programming. An interlaced 3D switch boxes and two‐dimensional (2D) switch boxes placement topology is also presented in this paper to design the 3D FPGA architecture for area efficiency purpose. The 3D place and route tool and TSMC 0.18‐µm CMOS process parameters are used to support building the experimental flow for verification. Performance evaluation shows that about 50% storage memory reduction can be obtained by using the proposed SGM‐based switch design approach. Additionally, compared with conventional architectures of 2D FPGA, the proposed scheme based on interlaced switch boxes placement approach can approximately achieve 20% delay‐power product improvement and 43% area‐delay product reduction. Copyright © 2010 John Wiley & Sons, Ltd.