3D Charge-trapping Flash Memory Research Articles

String-level compact modeling for dynamic operation and transient analysis of 3D charge trapping flash memory

In this article, we propose a string-level compact model, which is based on accurate and seamless channel electrostatic potential, for dynamic operation of 3D charge trapping flash (CTF) memory. First, we introduce a unit cell model for 3D CTF memory structure based on a conventional BSIM-CMG model using an extended netlist of equivalent circuits which describe the gate-all-around (GAA) structure composed of a metal gate, a blocking oxide, a charge trapping layer, and a tunneling oxide. Then, a string-level compact model is proposed, implying three advantages of inter-cell behaviors, seamless channel potential and process variation. To enhance the accuracy of the model behavior, extended model parameters are extracted showing good agreement with experimental data, such as I-V characteristics, program/erase speed, and incremental step pulse programming (ISPP). Furthermore, to predict channel electrostatic potential more precisely, we verify simulation program with integrated circuit emphasis (SPICE) simulation results of positively and negatively boosted channels comparing them with technology computer-aided design (TCAD) simulation results. Finally, we demonstrate that the proposed model can be efficiently applied to circuit simulation for analysis of the disturbance or failure mechanism and would equip the circuit designers and system architects with an effective tool for design optimization of 3D CTF memory devices.

PVSensing: A Process-Variation-Aware Space Allocation Strategy for 3D NAND Flash Memory

Three-dimensional (3D) flash memory is an emerging memory technology that enables a number of improvements to conventional planar NAND flash memory, including larger capacity, less program disturb, and lower access latency. Despite these advantages, 3D flash memory brings a number of new challenges. First, in 3D flash memory, NAND strings punch through multiple stacked layers to form the 3D infrastructure. Current etching process is unable to manufacture perfect channels with identical feature size. Second, with more stacked layers, the cell current in 3D flash memory is only 20% compared to planar flash memory, making it difficult to give a reliable sensing margin. These issues are affected by process variation, and they pose threats to the integrity of data stored in 3D flash memory. This article present <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">PVSensing</i> , a process-variation-aware space allocation strategy for open-channel SSD with 3D charge-trap flash memory. PVSensing is a novel hardware and file system interface that can transparently allocate physical space in the presence of process variation. PVSensing utilizes the rich functionalities provided by the system infrastructure of open-channel SSD to reduce the uncorrectable bit errors. Three reliability enhancement strategies (i.e., the adaptive creation of fault cubes, the physical block mining, and the live migration of write requests) are proposed. We demonstrate the viability of the proposed technique using a set of extensive experiments. Experimental results show that PVSensing can effectively reduce uncorrectable bit errors, and improve the reliability of critical data with negligible extra erase operations in comparison with representative schemes.

Effect of charge trap layer thickness on the charge spreading behavior within a few seconds in 3D charge trap flash memory

Charge spreading behavior within a few seconds, referred to as early retention, was comprehensively investigated in 24 word-line stacked tube-type 3D NAND flash memory. We thoroughly explored the charge spreading behavior from the perspectives of both electron and hole spreading in 3D NAND flash memory with different charge trap layer thicknesses at various programming and erasing levels for solid and checkerboard patterns to provide guidelines for minimizing and optimizing the charge spreading.

An Erase Efficiency Boosting Strategy for 3D Charge Trap NAND Flash

Owing to the fast-growing demands of larger and faster NAND flash devices, new manufacturing techniques have accelerated the down-scaling process of NAND flash memory. Among these new techniques, 3D charge trap flash is considered to be one of the most promising candidates for the next-generation NAND flash devices. However, the long erase latency of 3D charge trap flash becomes a critical issue. This issue is exacerbated because the distinct transient voltage shift phenomenon is worsened when the number of program/erase cycle increases. In contrast to existing works that aim to tackle the erase latency issue by reducing the number of block erases, we tackle this issue by utilizing the “multi-block erase” feature. In this work, an erase efficiency boosting strategy is proposed to boost the garbage collection efficiency of 3D charge trap flash via enabling multi-block erase inside flash chips. A series of experiments was conducted to demonstrate the capability of the proposed strategy on improving the erase efficiency and access performance of 3D charge trap flash. The results show that the erase latency of 3D charge trap flash memory is improved by 75.76 percent on average even when the P/E cycle reaches $10^{4}$ .

Low-temperature post-deposition annealing investigation for 3D charge trap flash memory by Kelvin probe force microscopy

The influence of post-deposition annealing (PDA) temperature condition on charge distribution behavior of HfO2 thin films was systematically investigated by various-temperature Kelvin probe force microscopy technology. Contact potential difference profiles demonstrated that charge storage capability shrinks with decreasing annealing temperature from 1,000 to 500 °C and lower. Compared to 1,000 °C PDA, it was found that 500 °C PDA causes deeper effective trap energy level, suppresses lateral charge spreading, and improves the retention characteristics. It is concluded that low-temperature PDA can be adopted in 3D HfO2-based charge trap flash memory to improve the thermal treatment compatibility of the bottom peripheral logic and upper memory arrays.

Future Prospects of NAND Flash Memory Technology—The Evolution from Floating Gate to Charge Trapping to 3D Stacking

NAND Flash memory has scaled at phenomenal speed in the last decade and conventional floating gate (FG) Flash memory has now commenced volume production in the 2X nm node. Despite this stunning success, the technology challenges are formidable below 20 nm. Charge-trapping (CT) devices are promising to scale beyond 20 nm but below 10 nm both CT and FG devices hold too few electrons for robust MLC (Multi-level Cell, or more than one bit storage per cell) storage. The simpler structure and its more robust storage (not sensitive to tunnel oxide defects since charges are stored in deep trap levels) also make CT suitable for 3D stacking. Optimistically, 3D CT Flash memory may allow the density increase to continue for at least another decade beyond the 1X nm node. In this paper, we review the current status of FG devices, their scaling challenges, and the operation principles of CT devices and several variations such as TANOS and BE-SONOS. We will then discuss various 3D memory architectures, technology challenges and address the poly-silicon thin film transistor (TFT) issues.

State-of-the-art flash memory devices and post-flash emerging memories

Although conventional Floating gate (FG) flash memory has recently gone into the 2X nm node, the technology challenges are formidable below 20 nm. Charge-trapping (CT) devices are promising to scale beyond 20 nm but below 10 nm both CT and FG devices hold too few electrons for robust MLC (multi-level cell, or more than one bit storage per cell) storage. However, due to the simpler structure and its more robust storage (not sensitive to tunnel oxide defects since charges are stored in deep trap levels), CT is much more desirable than FG in 3D stackable Flash memory. Optimistically, 3D CT Flash memory may allow the density increase to continue for at least another decade beyond the 1Xnm node. In this paper, we review the current status of FG devices, their scaling challenges, and the operation principles of CT devices and several variations such as MANOS and BE-SONOS. We will then discuss various 3D memory architectures, technology challenges and address the poly-silicon thin film transistor (TFT) issues. Devices that do not rely on charge storage are naturally not limited by the number of electrons, thus promise further scaling below 10 nm. Several of the most promising post-flash era devices, their operation principle and critical issues are reviewed. (One of them, phase change memory, will be covered in a separate article thus not included here.) Their potential applications and challenges for 3D stacking are critically examined.

Overview of Advanced 3D Charge-trapping Flash Memory Devices

AbstractAlthough conventional floating gate (FG) Flash memory has already gone into the sub-30 nm node, the technology challenges are formidable beyond 20nm. The fundamental challenges include FG interference, few-electron storage caused statistical fluctuation, poor short-channel effect, WL-WL breakdown, poor reliability, and edge effect sensitivity. Although charge-trapping (CT) devices have been proposed very early and studied for many years, these devices have not prevailed over FG Flash in the &gt; 30nm node. However, beyond 20nm the advantage of CT devices may become more significant. Especially, due to the simpler structure and no need for charge storage isolation, CT is much more desirable than FG in 3D stackable Flash memory. Optimistically, 3D CT Flash memory may allow the Moore's law to continue for at least another decade. In this paper, we review the operation principles of CT devices and several variations such as MANOS and BE-SONOS. We will then discuss 3D memory architectures including the bit-cost scalable approach. Technology challenges and the poly-silicon thin film transistor (TFT) issues will be addressed in detail.