32-bit Bus Research Articles

Exploration of Word Width and Cluster Size Effects on Tree-Based Embedded FPGA Using an Automation Framework

This paper introduces a novel framework that automates and accelerates the development of embedded Field Programmable Gate Arrays (eFPGAs). The proposed solution is considered as the first environment for tree-based eFPGA implementation including software, hardware and loader. The developed framework allows users to generate eFPGA architecture in the form of hardware description language using Physical Design Flow (PDF) tool. It is a powerful tool that can produce a wide variety of designs ranging from small eFPGA to complex eFPGA. The bit file description of practical application is done in parallel, simultaneously and rapidly by the suggested Computer Aided Design (CAD) tools. The Loader, called Multi-Level Loader (MLL), is also provided to inject the bits into the corresponding SRAMs. Our framework is widely explored by modifying the data width. This research proves that data width equal to 17 has the best trade-off between performance, area and static power. However, it is penalized for buses having data length greater than 32. The experimentation demonstrates that a data width equal to 12 is the best for a 32-bit bus. Automation and significant acceleration of the eFPGA development cycle are also achieved in this study. A set of bench-marking applications with various multi-use purposes is mapped. The experimental results show the efficiency and flexibility of the proposed framework.

Hardware Implementation of AES Encryption Algorithm Based on FPGA

With the development of society, the information industry has attracted more and more attention by the state. Since the emergence of prism doors, it has made countries pay great attention to the direction of information security. The question about how to protect information security has become an increasingly concerned issue. This paper introduces a widely used algorithm based on FPGA of symmetric encryption algorithm AES, because its key has three kinds of length 128bit, 192bit, 256bit, which can guarantee its difficulty in the crack, so it is relatively safe, this design can include encryption path and decryption path, you can also shield the decryption path and only include the encrypted path to reduce the use of resources in order to apply to resources insufficiently when the data is encrypted. Besides, this article can also be used for the key and data transmission using 32bit bus, multi-clock transmission. Through the Jtag Uart module to achieve the computer and embedded system communication, you can use it in the IDE integrated environment to achieve the program window to debug and monitor.

A novel memory management method for multi-core processors

This study examines a multicore processor based on a system-on-chip (SoC) and configured by a Tensilica Xtensa® LX2. The multicore processor is a heterogeneous, configurable dual-core processor. In this study, one core was used as the host to control the processor chip, and the other was used as a slave to extend digital signal processing applications. Each core not only owned its local memory, but also shared common data memory. In addition, the proposed multicore processors had a virtual memory. This additional memory supported the processor by enabling it to easily manage complex programs; it also allowed the two cores to access data from the unified data memory of different tasks. For bus management, a bus arbitration mechanism was added to handle the cores and to distribute the priority of asynchronous access requests. The benefits of the proposed structure include avoiding hardwired memory and reducing interface handshaking. To verify the proposed processor, it was simulated on the model level using a Petri net graph, and on the system level using ARM SoC designer tools. In the performance simulation, we found that the lowest latency-to-cost ratios were achieved using a 32-bit bus interface and a 4-entry data queue.

A digital signal processor-based pulse programmer with performance of run-time information handling for magnetic resonance imaging

A pulse programmer for magnetic resonance imaging based on a digital signal processor (DSP) is described. The pulse programmer not only implements event triggering and control line generation, but also performs the run-time information handling. The DSP, which has features that include a 32-bit data bus, a 24-bit address bus and a clock rate of 60 MHz, is used as the sequence operator. The DSP connects the field programmable gate array (FPGA) devices of all the spectrometer modules via its external bus, and manipulates the operation of each module via setting the control port of the corresponding FPGA. In addition, the run-time information of the spectrometer, which includes the operation status of each module and the external triggers, can be obtained easily using the read instruction, and the operation exceptions of the spectrometer can be treated quickly via the DSP’s interrupt mechanism. Up to 32 control lines can be generated simultaneously in an event, and the minimum interval between successive events is 50 ns. The pulse sequence program is written in the C++ language and is mainly composed of several predefined procedures. The performance of the proposed pulse programmer is validated by multiple imaging experiments.

VERIFICATION OF UART IP CORE USING UVM

In the earlier era of electronics the UART (Universal asynchronous receiver/transmitter) played a major role in data transmission. This UART IP CORE provides serial communication capabilities, which allow communication with modems or other external devices. This core is designed to be maximally compatible with industry standard designs[4]. The key features of this design are WISHBONE INTERFACE WITH 8-BIT OR 32-BIT selectable data bus modes. Debug interface in 32-bit data bus mode. Register level and functional compatibility. FIFO operation. The design is verified using UVM methodology. The test bench is written with regression test cases in order to acquire maximum functional coverage.

The Design of Platform System for Measuring Bio-Signalwith Array Sensors

Platform system for measuring the bio-signal, especially Aptamer using array sensor is designed. This platform system is based on 32-bit RISC processor, AMBA bus, peripheral device and interface for array sensors. Array sensors measure a variation of capacitance value by reaction with Aptamer from bio-signal. Processor reduces noise from measured bio-signal and carries out bio-signal processing algorithm.

Novel low-power bus invert coding methods with crosstalk detector

In System-on-a-Chip designs, crosstalk effects cause serious problems, such as wire propagation delay, noise, and power dissipation. In this article, we propose two new bus coding methods to reduce the dynamic power dissipation and wire propagation delay on buses efficiently. The proposed methods reduce both the dynamic power dissipation and wire propagation delay more than the existing bus coding methods do. Experimental results show that the crosstalk detector bus invert (CDBI) method reduces coupling activity to 25.7% from 36.4% and switching activity to 4.5% from 8.5% on 8-bit to 32-bit data buses. It reduces total power dissipation more than the other bus coding methods when a load capacitance is more than 0.3 pF/bit with UMC 0.09-µm CMOS technology. The enhanced CDBI (ECDBI) coding method reduces coupling activity to 28.4% from 38.4% and switching activity to 10.1% from 14% on 8-bit to 32-bit data buses. It reduces total power dissipation more than the other bus coding methods when a load capacitance is more than 0.2 pF/bit with UMC 0.09-µm CMOS technology. For a 0.8 pF/bit load capacitance, both the proposed methods reduce total power use by 19.3–30.9% when systems are implemented with UMC 0.09-µm CMOS technology. Similarly, both the proposed methods also reduce total power consumption more than the other bus coding methods with TSMC 0.18-µm CMOS technology. Meanwhile, the CDBI and the ECDBI schemes reduce total propagation delay up to 31.8% and 34.2%, respectively, on 32-bit data buses.

Designing Efficient Codecs for Bus-Invert Berger Code for Fully Asymmetric Communication

Berger-invert code is a coding scheme proposed recently to protect communication channels against all asymmetric errors and to decrease power consumption. This brief proposes a modified encoding scheme of Berger-invert codes and a new design of encoding/decoding circuitry (a codec). Implementation results prove that the new approach reduces the codec area and power consumption, respectively, by up to 30% and 48% for a 32-bit bus and decreases the error rate by up to about 35% for a 6-bit bus.

Efficient RC low-power bus encoding methods for crosstalk reduction

In on-chip buses, the RC crosstalk effect leads to serious problems, such as wire propagation delay and dynamic power dissipation. This paper presents two efficient bus-coding methods. The proposed methods simultaneously reduce more dynamic power dissipation and wire propagation delay than existing bus encoding methods. Our methods also reduce more total power consumption than other encoding methods. Simulation results show that the proposed method I reduces coupling activity by 26.7–38.2% and switching activity by 3.7%–7% on 8-bit to 32-bit data buses, respectively. The proposed method II reduces coupling activity by 27.5–39.1% and switching activity by 5.3–9% on 8-bit to 32-bit data buses, respectively. Both the proposed methods reduce dynamic power by 23.9–35.3% on 8-bit to 32-bit data buses and total propagation delay by up to 30.7–44.6% on 32-bit data buses, and eliminate the Type-4 coupling. Our methods also reduce total power consumption by 23.6–33.9%, 23.9–34.3%, and 24.1–34.6% on 8-bit to 32-bit data buses with the 0.18, 0.13, and 0.09 μm technologies, respectively.

Delay-efficient bus encoding techniques

On-chip buses in deep-submicron designs have large propagation delay due to dominant coupling capacitance. As delay impacts system performance, several techniques have been proposed in the literature to minimize it. A common point in most of the existing techniques is to consider uniformly distributed random data, but propagation delay is data dependent and data is application dependent. Different applications may have different data behaviors. The existing techniques which consider uniformly distributed random data may not exploit the exact data behavior of an application and hence can give inferior performance results. By exploiting similarity in the data transmitted on on-chip buses, we propose three delay minimization techniques, namely, data packing (DPack), data permutation (DPerm), and data replication with shielding and two-phase transmission (RESTP). We show that for a 5-mm 32-bit on-chip bus in 90 nm CMOS technology, the DPack, DPerm, and RESTP techniques achieve more than 25%, 32%, and 51% delay savings, respectively, in both address and data buses. For a 32-bit bus, the DPack, DPerm, and RESTP techniques require 38, 34, and 48 wires, respectively.

Selective shielding technique to eliminate crosstalk transitions

With CMOS process technology scaling to deep submicron level, propagation delay across long on-chip buses is becoming one of the main performance limiting factors in high-performance designs. Propagation delay is very significant when adjacent wires are transitioning in opposite direction as compared to transitioning in the same direction. As opposite transitions on adjacent wires (called as crosstalk transitions ) have significant impact on propagation delay, several bus encoding techniques have been proposed in literature to eliminate such transitions. We propose selective shielding technique to eliminate crosstalk transitions. We show that the selective shielding technique requires ⌈3 n /2⌉ wires to encode a n -bit bus. SPICE simulations by considering 90nm technology nodes reveal that, for uniformly distributed random data, our technique achieves nearly 39% (21%) delay savings over 10 mm -length uncoded 32-bit bus for pipelined (nonpipelined) data transmission at the cost of nearly 7% energy overhead.

Joint Equalization and Coding for On-Chip Bus Communication

In this paper, we propose using joint equalization and coding to improve on-chip communication speeds by signaling at rates beyond the rate governed by resistance-capacitance (RC) delay of the interconnect. Operating beyond the RC limit introduces inter-symbol interference (ISI). We mitigate the effects of ISI by employing equalization. The proposed equalizer employs a variable threshold inverter whose switching threshold is modified as a function of past output of the bus. We demonstrate even higher speedups by combining equalization with crosstalk avoidance coding. Specifically, simulation results for a 10-mm 32-bit bus in 0.13-mum CMOS technology show that 1.28 speedup is achievable by equalization alone and 2.30 speedup is achievable by joint equalization and coding.

Coding for reliable on-chip buses: a class of fundamental bounds and practical codes

A reliable high-speed bus employing low-swing signaling can be designed by encoding the bus to prevent crosstalk and provide error correction. Coding for on-chip buses requires additional bus wires and codec circuits. In this paper, fundamental bounds on the number of wires required to provide joint crosstalk avoidance and error correction using memoryless codes are presented. The authors propose a code construction that results in practical codec circuits with the number of wires being within 35% of the fundamental bounds. When applied to a 10-mm 32-bit bus in a 0.13-μm CMOS technology with low-swing signaling, one of the proposed codes provides 2.14× speedup and 27.5% energy savings at the cost of 2.1× area overhead, but without any loss in reliability.

Coding for Reliable On-Chip Buses: A Class of Fundamental Bounds and Practical Codes

A reliable high-speed bus employing low-swing signaling can be designed by encoding the bus to prevent crosstalk and provide error correction. Coding for on-chip buses requires additional bus wires and codec circuits. In this paper, fundamental bounds on the number of wires required to provide joint crosstalk avoidance and error correction using memoryless codes are presented. The authors propose a code construction that results in practical codec circuits with the number of wires being within 35% of the fundamental bounds. When applied to a 10-mm 32-bit bus in a 0.13-mum CMOS technology with low-swing signaling, one of the proposed codes provides 2.14times speedup and 27.5% energy savings at the cost of 2.1times area overhead, but without any loss in reliability

Design of Parallel Image Compression Circuits for High-speed CMOS Image Sensors

We investigated parallel image compression circuits suitable for integration in high-speed CMOS image sensors.We compared the coding efficiency and hardware complexity of several image compression algorithms that use 2-D DCTs using simulation and logic synthesis,and found that using 4$ imes$4 point 2-D DCT-based coding methods reduced hardware complexity and improved coding efficiency.We developed a parallel processing architecture for on-sensor image compression that use a processing element array and a data-buffering scheme for parallel data-output.We constructed a prototype 256 $ imes$ 256 pixel high-speed CMOS image sensor chip that integrates 16 image compression-processing elements and uses 0.25-$\mu$m CMOS technology.The area of the image compression circuits is 80\% of the image array with 15 $\mu$m square pixels.The entire chip could be operated at a clock frequency of 53.6 MHz,and high-speed images compressed by a factor of four could be read out at 10,000 fps using a 32-bit parallel bus.

Design of Parallel Image Compression Circuits for High-speed CMOS Image Sensors

We investigated parallel image compression circuits suitable for integration in high-speed CMOS image sensors.We compared the coding efficiency and hardware complexity of several image compression algorithms that use 2-D DCTs using simulation and logic synthesis,and found that using 4$ imes$4 point 2-D DCT-based coding methods reduced hardware complexity and improved coding efficiency.We developed a parallel processing architecture for on-sensor image compression that use a processing element array and a data-buffering scheme for parallel data-output.We constructed a prototype 256 $ imes$ 256 pixel high-speed CMOS image sensor chip that integrates 16 image compression-processing elements and uses 0.25-$\mu$m CMOS technology.The area of the image compression circuits is 80\% of the image array with 15 $\mu$m square pixels.The entire chip could be operated at a clock frequency of 53.6 MHz,and high-speed images compressed by a factor of four could be read out at 10,000 fps using a 32-bit parallel bus.

Scalable Architecture for SoC Video Encoders

Evolving video coding standards demand functional flexibility for implementations, not only at design time but also after fabrication. This paper presents a System-on-Chip design approach with a feasible combination of performance, scalability, programmability, area efficiency, and design time effort for a video encoder. The encoder is based on a homogeneous master-slave processor architecture. Each slave encodes a part of the frame in the Single Program Multiple Data (SPMD) data parallel model. Both shared and distributed memory architectures are presented. Design effort is reduced by identical program codes, automated assembly of software and hardware modules independent of the number and type of processors, as well as our flexible on-chip communication network called Heterogeneous IP Block Interconnection (HIBI). A case study implementation with two to ten simple ARM7 processors, 32-bit HIBI bus and non-optimized processor-independent software gives the performance from 6 to 53 fps for QCIF. The whole encoder area ranges from 173 to 770 kgates excluding the memories. The relation scales reasonably well to systems with more powerful processors and optimized code. The optimization of the communication network shows that with more than six slaves even a serial HIBI connection with 100 MHz speed is feasible. HIBI and the parallelization approach allow exploration and optimization of the communication both at the application and architecture layers.

Coding for system-on-chip networks: a unified framework

Global buses in deep-submicron (DSM) system-on-chip designs consume significant amounts of power, have large propagation delays, and are susceptible to errors due to DSM noise. Coding schemes exist that tackle these problems individually. In this paper, we present a coding framework derived from a communication-theoretic view of a DSM bus to jointly address power, delay, and reliability. In this framework, the data is first passed through a nonlinear source coder that reduces self and coupling transition activity and imposes a constraint on the peak coupling transitions on the bus. Next, a linear error control coder adds redundancy to enable error detection and correction. The framework is employed to efficiently combine existing codes and to derive novel codes that span a wide range of tradeoffs between bus delay, codec latency, power, area, and reliability. Using simulation results in 0.13-/spl mu/m CMOS technology, we show that coding is a better alternative to repeater insertion for delay reduction as it reduces power dissipation at the same time. For a 10-mm 4-bit bus, we show that a bus employing the proposed codes achieves up to 2.17/spl times/ speed-up and 33% energy savings over a bus employing Hamming code. For a 10-mm 32-bit bus, we show that 1.7/spl times/ speed-up and 27% reduction in energy are achievable over an uncoded bus by employing low-swing signaling without any loss in reliability.

A 1000 FPS at 128/spl times/128 vision processor with 8-bit digitized I/O

This paper presents a mixed-signal programmable chip for high-speed vision applications. It consists of an array of processing elements, arranged to operate in accordance with the principles of single instruction multiple data (SIMD) computing architectures. This chip, implemented in a 0.35-/spl mu/m fully digital CMOS technology, contains /spl sim/ 3.75 M transistors and exhibits peak performance figures of 330 GOPS (8-bit equivalent giga-operations per second), 3.6 GOPS/mm/sup 2/ and 82.5 GOPS/W. It includes structures for image acquisition and for image processing, meaning that it does not require a separate imager for operation. At the sensory side, integration and log-compression sensing circuits are embedded, thus allowing the chip to handle a large variety of illumination conditions. At the processing plane, analog and digital circuits are employed whose parameters can be programmed and their architecture reconfigured for the realization of software-coded processing algorithms. The chip provides, and accepts, 8-bit digitized data through a 32-bit bidirectional data bus which operates at 120 MB/s. Experimental results show that frame rates of 1000 frames per second (FPS) can be achieved under room illumination conditions; applications using exposures of about 50 /spl mu/s have been recently reached by using special illumination setups. The chip can capture an image, run approximately 150 two-dimensional linear convolutions, and download the result in 8-bit digital format, in less than 1 ms. This feature, together with the possibility of executing sequences of user-definable instructions (stored on a full-custom 32-kb on-chip memory), and storing intermediate results (up to 8 grayscale images) makes the chip a true general-purpose sensory/processing device.

Designing an S-LINK to PCI interface using an IP core

The S-LINK is a standard that defines the source and destination interfaces of a point-to-point data link. This standard is chosen for data transmission between front-end electronics and readout systems of some ongoing and future experiments at CERN, Geneva, Switzerland. This work presents the S32PCI64 interface that can move data from a 32-bit S-LINK Destination Card to any 32-bit or 64-bit PCI bus running at 33 MHz.