In mobile applications, power density highly affects mobility, cost, form factor, and battery time. To improve power density, high switching frequency operation is highly desirable for a power converter. However, with high switching frequency, switching power loss increases significantly, compromising efficiency and battery time. This article presents an on-chip 3-level DC-DC converter, using all NMOS devices as power switches, which reduces switching power loss and silicon cost. To facilitate the all-NMOS power stage operation and enhance the robustness to input supply variation, a 3-switch boost-strap gate driver is designed. Meanwhile, an interception coupling dead-time (ICDT) control is introduced to minimize dead-time related power loss. An integrated circuit prototype was fabricated using a 0.35 μm CMOS process. Robustly working with a variable input voltage from 3 to 6 V, it regulates a programmable power output from 0.4 to 1.6 V, with a maximum power efficiency of 85.5% over a full power range of 800 mW and a maximum power density of 1.07 W/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Thanks to the ICDT control, it achieves a 0.5 ns dead-time over a full-load range of 500 mA.
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