3-bit Errors Research Articles

Error-Correcting Unordered Codes and Hardware Support for Robust Asynchronous Global Communication

This paper introduces a new family of error-correction unordered (ECU) codes for global communication, called Zero-Sum. They combine the timing-robustness of delay-insensitive (i.e., unordered) codes with the fault-tolerance of error-correcting codes (providing 1-bit error correction or 2-bit detection). Two key features of the codes are that they are systematic, allowing direct extraction of data, and weighted, where the check field is computed as the sum of data index weights. A wide variety of weight assignments is shown to be feasible. Two practical enhancements are also proposed. The Zero-Sum <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> code extends error detection to 3-bit errors, or alternatively handles 2-bit detection and 1-bit correction. The Zero-Sum* code supports heuristic 2-bit correction, while still guaranteeing 2-bit detection, under different strategies of weight assignment. Detailed hardware implementations of the supporting components (encoder, completion detection, error corrector) are given, as well as an outline of the system microarchitecture. In comparison to the best alternative systematic ECU code, the basic Zero-Sum code provided better or comparable coding efficiency, with a 5.74%-18.18% reduction in average number of wire transitions for most field sizes. Several Zero-Sum* codes were also evaluated for their 2-bit error correction coverage; initial results are promising, where the best strategy corrected 52.92%-71.16% of all 2-bit errors for most field sizes, with only a moderate decrease in coding efficiency and increase in wire transitions. Technology-mapped pre-layout implementations of the supporting Zero-Sum code hardware were synthesized with the UC Berkeley ABC tool using a 90 nm industrial standard cell library. Results indicate that they have moderate area and delay overheads. In comparison, supporting hardware for the best nonsystematic ECU codes have 3.82-10.44× greater area for larger field sizes.

Soft decision decoding of block codes using received signal envelope in digital mobile radio

The codeword error rate (WER) performance of noncoherent frequency-shift keying with soft decision decoding of block codes using Chase's second algorithm (1972) is investigated in a Rayleigh fading channel. The received signal envelope is sampled and used as channel measurement information. The theoretical upper and lower bounds of the WER are derived, assuming independent Rayleigh envelope samples in a received block. When the Golay (23, 12, 7) code is used, soft decision decoding with 6-bit error correction capability (3-bit error and 3-bit erasure) requires an average signal-to-noise power ratio about 5 dB lower than that for minimum distance decoding with 3-bit error correction to obtain a WER=10/sup -3/. The effects of bit interleaving on the WER performance when fading envelope variation is slow compared to the bit rate are investigated through computer simulations.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Design and Application of a 20K Gate Array

This paper describes the design and architecture of a novel VLSI gate array in CMOS technology and its application for a 3-bit error checking and correcting (ECC) unit. The cell rows of the master are arranged without intermediate channels for routing (``sea of gates''). This scheme can be utilized to build large macro cells and functional blocks like data paths or systolic array cells which are very area consuming to realize in conventional gate arrays. In addition, special pull-up/pull-down cells are included on the chip which can be used for data buses and timing circuits. The technology used is an advanced p-well CMOS process with 1.8-µm geometric channel lengths and a two-layer metallization. There are 260 programmable pads for input/output functions and 20 additional power pads (280 pads in total). Depending on the logic, circuits with up to 25 000 gates can be realized with this device.

A Software Technique for Diagnosing and Correcting Memory Errors

A software diagnostic that eliminates 2-bit and some 3-bit errors is described. The diagnostic procedure tests memory for errors that cannot be corrected by ECC (error correcting code): single error correct, double error detect. When an uncorrectable error is found, the diagnostic attempts to reduce it to a I-bit error. This is done either by reconfiguring the memory to distribute failing bits across different ECC words or by replacing the failing chip with a spare. The result is that memory cards that previously had to be replaced can now continue to function. Thus, the life of memory cards can be prolonged. The diagnostic can also perform preventive maintenance when run in an alternate mode. In this mode, all combinations of the memory are tested to determine if there is reserve. Reserve is defined as: 1) The capability of reconfiguring the card to obtain another functional state of memory (in addition to the current operational state), or 2) The availability of functional spare chips that have not been used. Preventive maintenance is by replacing cards that have no reserve. Then, memory operation can continue error free.