2nd-order DeltaSigma Modulator Research Articles

A low-power CT 2nd order Delta Sigma modulator using a new design methodology for biomedical applications

This paper presents a low-power second-order continuous-time (CT) Delta-Sigma Modulator (DSM) using a new design methodology for biomedical applications. The proposed design methodology first implements a target block with the highest power consumption at a transistor level before optimizing the DSM coefficients. We are also able to reduce the area usage by appropriate limitations on the DSM range in the proposed design process. The DSM was implemented using the genetic algorithm (GA) and appropriate chopping techniques in our design process. The design was implemented in 0.18um CMOS technology by using a 0.083 mm2 layout, with a maximum SNDR and dynamic range of 94.28 and 100 dB, respectively, for a 2 kHz bandwidth and 32.34uW power consumption.

Development and evaluation of capacitance detection ASIC for three-axis common electrode type capacitive accelerometer

A capacitance detection CMOS ASIC has been developed for three-axis common electrode type capacitive accelerometers. The ASIC contains an analog output switched capacitor circuit and a digital output 2nd order deltasigma modulator. The circuits were driven by three or six phase clocks for three-axis detection. The characteristics of the circuits were evaluated by a variable capacitor and a three-axis capacitive accelerometer. A novel compensation method was proposed to reduce the sensitivity dependence on Z-axis acceleration. The three-axis output voltages of the switched capacitor circuits were proportional to three-axis accelerations. The offset and sensitivity of the 2nd order delta-sigma modulator can be calibrated by outer voltages. The sensitivities of 1.5V/G and 20kHz/G were obtained respectively when the circuits were combined with a commercial available three-axis capacitive accelerometer.