2DEG FET Research Articles

An accurate HJFET current–voltage model including temperature dependence for a circuit simulator

We present a new hetero-junction FET (HJFET) current–voltage ( I– V) model intended for implementation with a large signal simulator. The developed model takes into account the temperature dependence of drift current, diffusion current and gate diode current. The drift current model is based on our previous reported model [Hida H, Itoh T, Ohta K. An accurate dc model of 2-DEG FET for implementation on a circuit simulator. IEEE Electron Device Lett 1986;7:393–395.], which is based on gradual channel approximation taking into account the nonlinear field dependence of electron velocity. We found through measurements that transconductance, g m, drain conductance, g D, and threshold voltage, V T, vary as linear functions of temperature. To describe the dependence, we introduced linear functions of temperature into the g m, g D and V T descriptions. We also added the temperature dependence description to the diode current model and the diffusion current model. Although our model describes the temperature dependence using quite simple formulas, the simulated results agree well with the measurements.

Pseudomorphic 2DEG FET IC's for 10 Gb/s optical communication systems with external optical modulation

An optical modulator driver IC and a preamplifier IC for 10 Gb/s optical communication systems are developed using AlGaAs/InGaAs/GaAs pseudomorphic two-dimensional electron gas (2DEG) FETs with a gate length of 0.35 mu m. The optical modulator driver IC operates at a data rate up to 10 Gb/s with an output voltage swing of more than 4 V/sub p-p/. The bandwidth for the amplifier IC is 13.0 GHZ with ab 47 dB- Omega transimpedance gain. In addition, optical transmission experiments with external optical modulation using these ICs have successfully been carried out at 10 Gb/s. >

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A novel 2DEGFET model based on the parabolic velocity-field curve approximation

A new model for selectively doped heterostructure two-dimensional electron gas (2DEG) FET's has been proposed. In order to take into account the strong field dependence of the 2DEG mobility, a parabolic approximation is employed for a velocity-field curve below a velocity saturation field. The nonlinear field dependence of parasitic resistances has also been considered, which is of great importance for a more accurate description of actual FET characteristics. The proposed FET model is very useful for a digital IC design, since it has fewer fitting parameters and gives a smooth fit to measured data. Good agreement between the calculated drain current-voltage characteristics and the experimental characteristics, both for short-gate FET's and for long-gate FET's, demonstrates the validity of the present model. In addition, it has been recently found from the analysis that a transconductance compression is possible caused by a current limitation, due to hot electrons in the source-to-gate region, even though the n-(AlGa)As layer is totally depleted.

An accurate dc model of 2-DEG FET for implementation on a circuit simulator

An accurate dc model for FET's using two-dimensional (2- D) carrier gas flow adjacent to the heterointerface is described. The model, based on novel empirical velocity-field curve, also takes into consideration a parallel conduction in a selectively doped layer. In addition, it depends primarily on physical rather than empirical parameters. The calculated results are in excellent agreement with experimental data, even for short-channel 2-D electron gas (2-DEG) FET's at 77 K. The present model will therefore be a promising candidate for implementation on a circuit simulator.

A new low-noise AlGaAs/GaAs 2DEG FET with a surface undoped layer

A high-performance N-AlGaAs/GaAs selectively doped two-dimensional electron gas (2DEG) FET with a surface undoped layer has been designed and demonstrated. Simple analysis based on the short-channel approximation revealed that an increase in a total layer thickness between a gate electrode and 2DEG at a hetero-interface results in a higher cutoff frequency and a lower noise figure than conventional 2DEG FET's. This is because the gate capacitance can be markedly reduced without a significant decrease in the transconductance owing to a parasitic source resistance. The surface undoped layer intentionally employed in this work can permit the total layer thickness to increase, i.e., the gate capacitance to reduce, without changes in the 2DEG density and in the source resistance. This structure also gives high gate breakdown voltage because of a small neutral region in n- (AlGa)As and a low surface electron field, which possibly yields excellent performance 2DEG FET's for practical use. Fabricated (AlGa)As/ GaAs 2DEG FET's exhibited noticeable room-temperature performances of 0.95-dB noise figure with 10.3-dB associated gain at 12- and 45-GHz cutoff frequency. These are the best data ever reported for 0.5-µm gate length FET's.

AlGaAs/GaAs 2-DEG FET's fabricated from MO-CVD Wafers

A transconductance (g <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</inf> ) of as high as 330 mS/mm is obtained from wafers grown by MO-CVD in which triethyl gallium and triethyl aluminum are used as organometallic compounds. A comparison between the experimental and theoretical results is made for the dependence of g <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</inf> on the thickness of the AlGaAs layer. The saturation of velocity of 2-DEG determined from the drain I-V characteristics is found to be as high as 2 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> cm/s regardless of the absence of the undoped spacer layer.

Control of threshold voltage of AlGaAs/GaAs 2DEG FET's through heat treatment

Threshold voltage controls of Ni/Ti/Au gate and Ti/Au gate 2DEG AlGaAs/GaAs FET's through only heat treatment are investigated. Ni/Ti/Au gate FET's vary over quite a wide range from a depletion mode to an enhancement mode without degradation of FET characteristics after heat treatment at 300°C. The same experiment is made for Ti/Au gate FET's, but the threshold voltage change is negligibly small. It is confirmed that Ni/Ti/Au can be used as the gate metal for E-FET and Ti/Au as the gate metal for D-FET under simultaneous heat treatment. In addition, a mechanism for penetrating the barrier metal into the underlying layer is discussed.