1T1R Resistive Random Access Memory Research Articles

Improved Arithmetic Performance by Combining Stateful and Non‐Stateful Logic in Resistive Random Access Memory 1T–1R Crossbars

Computing‐in‐memory (CIM) is a promising approach for overcoming the memory‐wall problem in conventional von‐Neumann architectures. This is done by performing certain computation tasks directly in the storage subsystem without transferring data between storage and processing units. Stateful and non‐stateful CIM concepts are recently attracting lots of interest, which are demonstrated as logical complete, energy efficient, and compatible with dense crossbar structures. However, sneak‐path currents in passive resistive random access memory (RRAM) crossbars degrade the operation reliability and require the usage of active 1 Transistor–1 Resistance (1T‐1R) bitcell designs. In this article, the arithmetic performance and reliability are investigated based on experimental measurements and variability‐aware circuit simulations. Herein, it is aimed for the evaluation of logic operations specifically with fully integrated 1T–1R crossbar devices. Based on these operations, an N‐bit full adder with optimized energy consumption and latency is demonstrated by combining stateful and non‐stateful CIM logic styles with regard to the specific conditions in active 1T–1R RRAM crossbars.

Ultrathin HfO2/Al2O3 bilayer based reliable 1T1R RRAM electronic synapses with low power consumption for neuromorphic computing

Neuromorphic computing requires highly reliable and low power consumption electronic synapses. Complementary-metal-oxide-semiconductor (CMOS) compatible HfO2 based memristors are a strong candidate despite of challenges like non-optimized material engineering and device structures. We report here CMOS integrated 1-transistor-1-resistor (1T1R) electronic synapses with ultrathin HfO2/Al2O3 bilayer stacks (<5.5 nm) with high-performances. The layer thicknesses were optimized using statistically extensive electrical studies and the optimized HfO2(3 nm)/ Al2O3(1.5 nm) sample shows the high reliability of 600 DC cycles, the low Set voltage of ∼0.15 V and the low operation current of ∼6 µA. Electron transport mechanisms under cycling operation of single-layer HfO2 and bilayer HfO2/Al2O3 samples were compared, and it turned out that the inserted thin Al2O3 layer results in stable ionic conduction. Compared to the single layer HfO2 stack with almost the same thickness, the superiorities of HfO2/Al2O3 1T1R resistive random access memory (RRAM) devices in electronic synapse were thoroughly clarified, such as better DC analog switching and continuous conductance distribution in a larger regulated range (0–700 µS). Using the proposed bilayer HfO2/Al2O3 devices, a recognition accuracy of 95.6% of MNIST dataset was achieved. These results highlight the promising role of the ultrathin HfO2/Al2O3 bilayer RRAM devices in the application of high-performance neuromorphic computing.

Sensitivity of HfO2-based RRAM Cells to Laser Irradiation

Today, the technology of resistive random access memory is used as a non-volatile memory. In this paper we investigate in details the sensitivity of the TiN/Ti/Al:HfO2/TiN-based 1T-1R resistive random access memory cells implemented in a 250 nm CMOS IHP technology to the laser irradiation. Experimental results show that the laser irradiation can influence the resistive state of RRAM cells significantly, i.e. precisely localized optical faults can be successfully injected. We focus on the selection of the configurable parameters of the laser station and their influence on the success of optical Fault Injections. Additionally, we localize sensitive areas of attacked chips. Based on the determined sensitive areas we show that metal fillers atop memory cells influence on success of optical fault injection attacks.

Automated Testing Algorithm for the Improvement of 1T1R ReRAM Endurance

One of the most attractive types of novel nonvolatile memory concepts is resistive random access memory (ReRAM) based on a reversible (“soft”) dielectric breakdown effect. The interest is caused by combining simple architecture with promising performance: excellent scalability, nanosecond speed, long data retention, and low power consumption. However, the commercialization of this type of memory is retarded mainly due to serious drawbacks: high cell-to-cell variability of switching parameters and limited endurance related to the ionic origin of resistive switching effect coupled with the problem of voltage overshooting. In particular, these issues complicate the examination of test samples because during the lifespan of memory cells, and the permanent reselection of test switching parameters is required. This challenge can be overcome by developing a measurement technique that combines careful testing of every single structure and the ability to test a large number of test structures. As such a technique, we propose an automated testing algorithm that automatically avoids voltage overshooting and provides an effective way of characterization of cell-to-cell and cycle-to-cycle variability. It includes all stages of ReRAM cell operation, specifically electroforming, dc switching, and endurance testing in the pulsed mode. The developed technique allows on-the-fly restoring of the memory window in case of its degradation, making it possible to better understand the potential of the material stacks of the memory cell.

A CRP-Space-Extended RRAM PUF With In-Cell Zero-Overhead Salicide-Blocked Contact

In this brief, we present an ultracompact physical unclonable function (PUF) based on the resistive random access memory (RRAM) with the in-cell salicide-blocked (SAB) contact. Different from most previously reported RRAM PUFs with only the RRAM cell's high-resistance state (HRS) utilized as the static entropy, its low-resistance state (LRS) is enabled with the proposed SAB contact resistance as a novel entropy source. Concretely, by adding a photolithography mask of “SAB” that widely exists in standard CMOS process to the source/drain contact of the mainstream one-transistor-one-resistor (1T1R) RRAM cell's access transistor, an SAB contact featuring large resistance stochasticity can be formed with zero design overhead of silicon area. With the SAB contact resistance connected in series, both HRS and LRS can be well-exploited to generate much more challenge-response pairs (CRPs), leading to significantly extended CRP space. In addition, the proposed RRAM PUF with in-cell SAB contact is validated using 0.18- μm standard CMOS process plus postprocessing steps for RRAM devices, and the normalized bitcell area is reported to be 77 F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /bit. By varying the operating temperature from -50 °C to 150 °C, the worst case bit error rate (BER) is measured to be 0.13% at 150 °C. Moreover, the excellent randomness of the proposed implementation is verified by passing both the National Institute of Standards and Technology (NIST) test and the autocorrelation function (ACF) test.

Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing

Accomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, we implemented this feature on 4-kbit 1T1R RRAM arrays by tuning the programming parameters of the multi-level incremental step pulse with verify algorithm (M-ISPVA). The optimized set of parameters was assessed by comparing its results with a non-optimized one. The optimized set of parameters proved to be an effective way to define non-overlapped conductive levels due to the strong reduction of the device-to-device variability as well as of the cycle-to-cycle variability, assessed by inter-levels switching tests and during 1k reset-set cycles. In order to evaluate this improvement in real scenarios, the experimental characteristics of the RRAM devices were captured by means of a behavioral model, which was used to simulate two different neuromorphic systems: an 8×8 vector-matrix-multiplication (VMM) accelerator and a 4-layer feedforward neural network for MNIST database recognition. The results clearly showed that the optimization of the programming parameters improved both the precision of VMM results as well as the recognition accuracy of the neural network in about 6% compared with the use of non-optimized parameters.

Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory

Nonvolatile memory (NVM)-based computing in-memory (CIM) is a promising solution to data-intensive applications. This work proposes a 2T2R resistive random access memory (ReRAM) architecture that supports three types of CIM operations: 1) ternary content addressable memory (TCAM); 2) logic in-memory (LiM) primitives and arithmetic blocks such as full adder (FA) and full subtractor; and 3) in-memory dot-product for neural networks. The proposed architecture allows the NVM operations in both 2T2R and conventional 1T1R configurations. The proposed LiM full adder (LiM-FA) improves the delay, the static power, and the dynamic power by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3.2\times $ </tex-math></inline-formula> , <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.2\times $ </tex-math></inline-formula> , and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.6\times $ </tex-math></inline-formula> , respectively, compared with state-of-the-art LiM-FAs. Furthermore, based on different optimization techniques and robustness analysis, a lower precharge voltage is set for each mode. This reduces the TCAM search energy and 1T1R ReRAM access energy by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.6\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.14\times $ </tex-math></inline-formula> , respectively, compared with the case without optimizations.

Unsupervised Learning on Resistive Memory Array Based Spiking Neural Networks.

Spiking Neural Networks (SNNs) offer great potential to promote both the performance and efficiency of real-world computing systems, considering the biological plausibility of SNNs. The emerging analog Resistive Random Access Memory (RRAM) devices have drawn increasing interest as potential neuromorphic hardware for implementing practical SNNs. In this article, we propose a novel training approach (called greedy training) for SNNs by diluting spike events on the temporal dimension with necessary controls on input encoding phase switching, endowing SNNs with the ability to cooperate with the inevitable conductance variations of RRAM devices. The SNNs could utilize Spike-Timing-Dependent Plasticity (STDP) as the unsupervised learning rule, and this plasticity has been observed on our one-transistor-one-resistor (1T1R) RRAM devices under voltage pulses with designed waveforms. We have also conducted handwritten digit recognition task simulations on MNIST dataset. The results show that the unsupervised SNNs trained by the proposed method could mitigate the requirement for the number of gradual levels of RRAM devices, and also have immunity to both cycle-to-cycle and device-to-device RRAM conductance variations. Unsupervised SNNs trained by the proposed methods could cooperate with real RRAM devices with non-ideal behaviors better, promising high feasibility of RRAM array based neuromorphic systems for online training.

Efficient Implementation of Boolean and Full-Adder Functions With 1T1R RRAMs for Beyond Von Neumann In-Memory Computing

In-memory computing architecture is an emerging revolutionary computing paradigm that can break the von Neumann bottleneck. Computing methodology and circuit codesign using the CMOS compatible 1T1R resistive random access memory (RRAM) integration structure is presented in this paper. Functionally complete Boolean logic and arithmetic functions are experimentally demonstrated. With a single 40-nm CMOS process 1T1R unit, each of the 16 binary logics can be realized in two logic steps with an additional readout step for cascading, which shows functional reconfiguration and low computational complexity. Up to 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> cycles of NAND and XOR logic operations are performed to validate the correctness and reliability. Moreover, several fundamental adder circuits are designed and experimentally demonstrated in 1T1R devices as the proof of concept of the 1T1R computing architecture. The adders proposed in this paper include a ripple-carry adder and its optimized design and a carry-select adder, which all show promising advantages in nonvolatility, computation speed, and circuit area. This paper reports the most complex yet efficient RRAM-based 8-bit addition function experimentally so far and lays a solid foundation for constructing the future in-memory computing architecture.

Proposing a Solution for Single-Event Upset in 1T1R RRAM Memory Arrays

Resistive random access memory (RRAM) is a promising emerging technology to provide nonvolatile and scalable data storage in advanced technologies. As a noncharge-based device, the intrinsic RRAM device is immune to single-event effects. However, single-event upset (SEU) due to the MOSFET in the one-transistor-one-RRAM (1T1R) array can be observed. A novel methodology, which can be easily integrated to the other memory system components, is proposed in this paper to detect and correct SEU in 1T1R RRAM memory array. Using the HfO x 1T1R RRAM array as an example, our simulation results show that, for an 8-Gb memory array, the proposed technique can detect and fix the soft errors induced by the heavy ion strikes with 0.66% increase in the chip area. Also, the suggested methodology minimally increases the energy consumption of the read and write operations by 0.2% and 0.1%, respectively.

A Method to Reduce Forming Voltage Without Degrading Device Performance in Hafnium Oxide-Based 1T1R Resistive Random Access Memory

In this paper, we discover an operation method that can effectively decrease the forming voltage in resistance random access memory (RRAM). Forming voltage can be reduced by either increasing the rising time of the forming-waveform or by increasing the temperature in the forming process. However, the resulting electronic RRAM characteristics after each of these methods differ. While increasing the rising time causes greater damage to the switching layer due to longer accumulation of charge, increasing temperature in the forming process does not. The high temperature-formed RRAM excels in retention and endurance tests, proving an effective means to decrease forming voltage.

The Role of Ti Buffer Layer Thickness on the Resistive Switching Properties of Hafnium Oxide-Based Resistive Switching Memories.

Ti/HfOx-based resistive random access memory (RRAM) has been extensively investigated as an emerging nonvolatile memory (NVM) candidate due to its excellent memory performance and CMOS process compatibility. Although the importance of the role of the Ti buffer layer is well recognized, detailed understanding about the nature of Ti thickness-dependent asymmetric switching is still missing. To realize this, the present work addresses the effects of Ti buffer layer thickness on the switching properties of TiN/Ti/HfOx/TiN 1T1R RRAM. Consequently, we have demonstrated a simple strategy to regulate the FORMING voltage, leakage current, memory window, and decrease the operation current, etc. by varying the thickness of the Ti layer on the HfOx dielectrics. Accordingly, controllable and reliable bipolar, complementary, and reverse bipolar resistive switching (BRS, CRS, and R-BRS) properties have been demonstrated. This work also provides the direction to avoid unwanted CRS properties during the first RESET operation by decreasing the FORMING voltage. Furthermore, the memory device shows good nonvolatility at ∼1 μA programming current by selecting a proper thickness of Ti buffer layer. To achieve reliable BRS properties for low power application, the operation current has been further optimized, whereas the memory device shows pulse endurance of more than 7 million cycles at a low pulse width of 50 ns and excellent data retention properties of more than 40 h at 150 °C measurement temperature.

Communication—Effect of a Self-Limited Reset Operation on the Reset Breakdown Characteristics of a Monolithically Integrated 1T1R RRAM

The reset breakdown of resistive random access memory (RRAM) significantly degrades device endurance. We suppressed reset breakdown by optimizing the reset operation in an HfO2-based 1T1R RRAM device. The effective gate-to-source voltage VGSeff is reduced by increasing the RRAM resistance during the reset operation. By applying the optimum VGS, we can both guarantee a sufficient reset current and suppress reset breakdown. The experimental results confirmed improved endurance characteristics without a degraded resistance ratio.

Electrical study of radiation hard designed HfO2-based 1T-1R RRAM devices

ABSTRACTIn this work the electrical performance of a radiation hard designed 1T-1R resistive random access memory (RRAM) device is investigated in DC (voltage sweep) and AC (pulsed voltage) modes. This new device is based on the combination of an Enclosed Layout Transistor (ELT) used as selector device and a TiN/ HfO2/ Ti/TiN RRAM stack used as resistive device. The high cell to cell variability in the DC mode makes it difficult to define an electrical gap between the High Resistive State (HRS) and the Low Resistive State (LRS). The strong reduction of the variability by the use of Incremental Step Pulse with Verify Algorithm (ISPVA) makes the later a mandatory programming approach. The Quantum Point Contact (QPC) model defines an energy barrier located in the rupture point of the filament in HRS. The compensation between the width and height variations of this barrier during cycling could explain the stability of HRS and LRS. The good performance of the proposed device using the ISPVA programming approach makes it a good candidate for Rad-Hard Non Volatile Memories integration.

Material insights of HfO2-based integrated 1-transistor-1-resistor resistive random access memory devices processed by batch atomic layer deposition.

With the continuous scaling of resistive random access memory (RRAM) devices, in-depth understanding of the physical mechanism and the material issues, particularly by directly studying integrated cells, become more and more important to further improve the device performances. In this work, HfO2-based integrated 1-transistor-1-resistor (1T1R) RRAM devices were processed in a standard 0.25 μm complementary-metal-oxide-semiconductor (CMOS) process line, using a batch atomic layer deposition (ALD) tool, which is particularly designed for mass production. We demonstrate a systematic study on TiN/Ti/HfO2/TiN/Si RRAM devices to correlate key material factors (nano-crystallites and carbon impurities) with the filament type resistive switching (RS) behaviours. The augmentation of the nano-crystallites density in the film increases the forming voltage of devices and its variation. Carbon residues in HfO2 films turn out to be an even more significant factor strongly impacting the RS behaviour. A relatively higher deposition temperature of 300 °C dramatically reduces the residual carbon concentration, thus leading to enhanced RS performances of devices, including lower power consumption, better endurance and higher reliability. Such thorough understanding on physical mechanism of RS and the correlation between material and device performances will facilitate the realization of high density and reliable embedded RRAM devices with low power consumption.

Resistive switching characteristics of integrated polycrystalline hafnium oxide based one transistor and one resistor devices fabricated by atomic vapor deposition methods

In this work, the bipolar resistive switching (RS) characteristics of polycrystalline hafnium oxide are studied in embedded 1 transistor-1 resistor (1T1R) resistive random access memory (RRAM) devices. The HfO2 films with varied thickness from 15 to 25 nm were grown by the atomic vapor deposition method at 400 °C. The HfO2 films are polycrystalline, as evaluated by applying atomic force microscopy and x-ray diffraction. In addition, current–voltage characteristics of the 1T1R devices were investigated. The forming voltages of 15 nm thick HfO2 films are about 4 V and increase gradually with increasing film thickness. A reproducible resistance switching behavior was observed with a high resistance ratio of ∼20 during DC cycling of 100 times. The observed SET and RESET voltages are about 1.2 and 1.6 V, respectively, indicating that the 1T1R RRAM device can be operated below 2 V. The current–voltage characteristics are discussed in the frame of the quantum point contact model.

Uniformity Improvement in 1T1R RRAM With Gate Voltage Ramp Programming

Uniformity is one of the most severe challenges for resistive random access memory (RRAM). In this letter, a novel programming scheme with gate voltage ramping (GVR) is proposed to improve the uniformity of RRAM in a one transistor and one resistor structure. In traditional operation, the gate of the access transistor is biased with a constant voltage and a sweeping voltage is applied to the source or drain during the SET (from HRS to LRS) and RESET (from LRS to HRS) processes. With the GVR scheme, the gate voltage V G is ramped and the source/drain are kept constant. A tight distribution of HRS can be achieved using GVR. Analysis of power generation in the RESET process of the GVR scheme reveals positive feedback from joule heating, which helps to accelerate filament rupture and results in a tendency to achieve full RESET. The intermediate resistance states commonly observed are effectively eliminated.

Single- and Multiple-Event Induced Upsets in &lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;${\rm HfO}_2/{\rm Hf}$&lt;/tex&gt;&lt;/formula&gt; 1T1R RRAM

Single-event upsets in 1T1R Resistive Random Access Memory (RRAM) structures are experimentally demonstrated by generating current transients in the access transistors of the memory cells. The relationship between the single-event upset threshold of the RRAM and the applied voltage is exponential, which is verified using TPA laser analysis and heavy-ion irradiation. Multiple-Event Upsets (MEUs) also occur, where individual ions incrementally change the RRAM's resistance until their cumulative effect causes an upset. Single-event models are presented that allow direct correlation of the voltage across the RRAM, caused by the ion-generated current transient, and the change in RRAM resistance. The RRAM is vulnerable only in the high resistance state, when a voltage capable of writing to the cell is applied to the bit line. This is approximately 0.5% of the memory element's operation time, leading to relatively low projected upset rates.