14nm FDSOI Technology Research Articles

On the Critical Role of Ferroelectric Thickness for Negative Capacitance Device-Circuit Interaction

This paper demonstrates the critical role that Ferroelectric (FE) layer thickness (tFE) plays in Negative Capacitance (NC) transistors connecting device and circuit levels together. The study is done through fully-calibrated TCAD simulations for a 14nm FDSOI technology node, exploring the impact of tFE on the figures of merit of n-type and p-type devices, voltage transfer characteristic (VTC) and noise margin of inverter as well as the speed of buffer circuits. First, we analyze the device electrical parameters (e.g., ION, SS, ION/IOFF and Cgg) by varying tFE up to the maximum level at which hysteresis in the I-V characteristic starts. Then, we analyze the deleterious impact of Negative Differential Resistance (NDR), due to the drain to gate coupling, demonstrating how it imposes an additional constraint limiting the maximum tFE. We show the consequences of NDR effects on the VTC and noise margin of inverter, which are essential components for constructing robust clock trees in any chip. We demonstrate how the considerable increase in the gate’s capacitance due to FE seriously degrades the circuit’s performance imposing further constraints limiting the maximum tFE. Further, we analyze the impact of tFE on the SRAM cell static performance metrics such hold noise margin (HNM), read noise margin (RNM) and write noise margin (WNM) at supply voltages of 0.7V and 0.4V. We demonstrate that the HNM and RNM in a NC-FDSOI FET based SRAM cell are higher then those of the baseline FDSOI FET based SRAM cell noise margin and further increase with tFE. However, the WNM in general follows a non monotonic trend w.r.t tFE, and the trend also depends on the supply voltage. Finally, we optimize the design of the SRAM cell considering overall performance metrics. All in all, our analysis provides guidance for device and circuit designers to select the optimal FE thickness for NCFETs in which hysteresis-free operations, reliability, and performance are optimized.

Dynamic variability in 14 nm FD-SOI MOSFETs and transient simulation methodology

The impact of the dynamic variability due to low frequency and RTN fluctuations on single MOSFET operation from 14nm FD-SOI technology is investigated for the first time. It is shown that the dynamic variability is enhanced as the rise time and the device area are reduced. Different simulation approaches were investigated to determine the best methodology for simulating the dynamic variability in Cadence circuit simulation tool. It is demonstrated that Monte-Carlo and periodic transient noise simulations are methodologies capable to reproduce accurately dynamic variability in Cadence.

(Invited) 14nm FDSOI Technology for High-Speed and Energy-Efficient CMOS

As CMOS technology scales down, two paths are pursued by the industry to overcome the fundamental limits of traditional planar bulk transistors. One is the introduction of a Tri-Gate or FinFET transistor at the 22 and 16 nm nodes [1, 2]. These architectures provide impressive drive currents per footprint at low supply voltages because of the 3-D conduction channel and excellent electrostatic control. Conversely, they have high gate and parasitic capacitances, proportional to the 3-D effective W increase, which negatively impacts both the speed and active power consumption. Alternatively FDSOI provides an evolutionary path. First introduced at the 28nm node [3], FDSOI includes excellent mismatch properties, a simplified planar manufacturing process vs 3-D finFET technology and capitalization of existing design techniques. It also extends the possibility of back biasing and therefore offers unique “smart” solutions for dynamic power optimization [4]. The technology presented in this paper furthers the appeal of FDSOI to the 14nm node [5]. Compared to the 28nm technology, new Front-End process elements include a dual SOI/SiGeOI N/P channel, a dual workfunction gate-first HKMG integration scheme and a dual in-situ doped Si:CP/SiGeB N/P raised source-drain [5]. Additionally hybrid bulk areas, formed before Shallow Trench Isolation (STI), provide a space for passive devices and ESD FETs to be built [6]. The strained-SiGe channel (cSiGe) is realized before STI patterning to avoid SiGeOI over-thinning linked to the Ge condensation process at active edges [7] (Fig.1). As shown in Fig.1, strain into the channel has been experimentally measured by Nano-Beam Electron Diffraction (NBED) : 1% compressive strain in the 6nm thin SiGeOI channel (25%Ge) is demonstrated. After gate patterning, a N/P dual spacer/dual epitaxy scheme is used, as illustrated in Fig.2.Since gate-to-drain capacitance (Cgd) is of high importance for the circuit speed and power, spacer, poly thickness and raised source-drain epitaxy (Fig.2) has been optimised to minimize Cgd down to ~0.3fF/µm for both n and pMOS devices. cSiGe and SiGeB source-drain implementation in 14nm FDSOI provides a large pMOS drive current enhancement when compared to FDSOI technology at the 28nm node. As a result of low Cgd and large pMOS drive current, 14FDSOI technology demonstrated in [5] a -20% delay gain with the Fan-Out 3 (FO3) RO inverters at the same static leakage and a 100mV Vdd reduction (0.8V vs 0.9V) over the 28nm FDSOI technology (Fig.3). From this previous work, the transistor performance has further progressed and the delay boost is now established at -34% with -100mV Vdd operation, as shown in Fig.3. It means >50% speed frequency in 14FDSOI at 0.8V Vdd vs 28FDSOI at 0.9V Vdd. These large performance enhancements over 28FDSOI make 14FDSOI as a leading edge technology for the 14nm node and a highly competitive technology for low voltage and energy efficient CMOS applications.

(Invited) 14nm FDSOI Technology for High-Speed and Energy-Efficient CMOS

This work presents a 14nm technology designed for high speed and energy efficient applications using FDSOI transistors. The specific process integration features of this technology are highlighted in this paper. The transistors have been strain-engineered to provide high drive current and optimally designed to achieve low parasitic capacitance. As a result, this 14nm FDSOI technology provides 0.55x area scaling and delivers +50% speed with -100mV Vdd supply voltage operation compared to the 28nm FDSOI technology.