10-bit Pipelined Analog-to-digital Converter Research Articles

LDO-Free Power Management System: A 10-bit Pipelined ADC Directly Powered by Inductor-Based Boost Converter With Ripple Calibration

This article presents a compact power management solution for a pipeline analog-to-digital converter (ADC), employing only a switching-mode power converter. By directly powering the ADC using a boost DC-DC converter, the power delivery network (PDN) exhibits an overall-high power efficiency. The proposed foreground ADC calibration calibrates the ripple error induced from the power converter, which obviates the need for well-regulated supply and reference voltage offered by low-efficiency linear low-dropout regulators (LDOs). A chip integrates the boost DC-DC converter and the pipelined ADC with an external power inductor. The prototype, implemented in 65-nm CMOS, occupies 2.34-mm2 of total active area (9.4% - ADC, 2.6% - power controller and switches, and 88% - output capacitance). In the measurement, the boost converter, switching at 31.25MHz, converts a 0.5V input to 1.2V and delivers 22.8mW of power to the pipeline ADC. The boost DC-DC converter supplies all voltage domains, including analog/digital power supply and reference. The resulting overall system power efficiency is 78.6%. Sampled at 500MS/s, the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 34.7/39.9dB without/with the ripple calibration for an input frequency of 177MHz, respectively.

Yield constrained automated design algorithm for power optimized pipeline ADC

Pipeline Analog to Digital Converter (ADC) design processes include several redesign steps to achieve the optimum solution. Hence, designers prefer to use automated algorithms for this purpose. In this paper, an automated algorithm for CAD tool is presented considering the trade-off between yield and power consumption for pipeline ADCs. This automated algorithm benefits from multiple degrees of freedom including the system level down to transistor level parameters, which helps CAD tools to find the optimized solution. It allows designers to choose an optimum scenario considering the trade-off between yield and power consumption. To evaluate the capabilities of this algorithm, a 10-bit pipeline ADC is designed and analyzed. This ADC has 10-bit resolution and 6.3 mW power, 91% yield, 55.3 dB SNDR and 58.8 dB SFDR, which are all in good agreement with the algorithm results. In comparison with similar designs it offers a competitive Figure of Merit (FOM), which proves the capability of this algorithm in finding the optimum solution.

A Self-Biased Current-Mode Amplifier With an Application to 10-bit Pipeline ADC

This paper presents a self-biased current-mode amplifier (CMAMP) suitable for a switched-capacitor circuit. The CMAMP uses a subthreshold-biased transimpedance stage as a current-sensing load, and minimizes static power dissipation by passing bias current only at the input stage. The first-order system behavior with single dominant pole gives stable phase margin without complicated frequency compensation. Self-biasing circuits automatically generate bias voltages to sustain performance over a wide range of supply voltage. The designed CMAMP is verified in a 10-bit pipeline analog-to-digital converter (ADC) fabricated in a 65-nm CMOS process. The ADC achieves a figure of merit of 14.3 fJ/c-s with a supply voltage of 0.6 V at 2.5 MS/s.

Design and Power Optimization of High-Speed Pipelined ADC with Programmable Gain Amplifier for Wireless Receiver Applications

This paper proposes a 10-bit 100 MS/s 20 MHz low power pipelined analog-to-digital converter (ADC) with switched capacitor based programmable gain amplifier (PGA) suitable for wireless receiver applications. In the proposed ADC the double loading problem caused in the first stage of 10-bit pipelined ADC is avoided. In order to minimize the power consumption, split-capacitor sharing correlated double sampling and op-amp sharing technique has been used. Using the technique, low-gain operational amplifiers (op-amps) can be employed to implement a low-power pipelined ADC. Switched capacitor topology based PGA occupies an area of 0.0031 mm2. Switched capacitor topology based PGA with the integration of 10-bit pipelined ADC consumes 25.54 mW of power at 100 MS/s from a 1.8 V power supply.

A low power time-interleaved 10-bit 250-MSPS charge domain pipelined ADC for IF sampling

A 10-bit 250-MSPS two-channel time-interleaved charge-domain (CD) pipelined analog-to-digital converter (ADC) is presented. MOS bucket-brigade device (BBD) based CD pipelined architecture is used to achieve low power consumption. An all digital low power DLL is used to alleviate the timing mismatches and to reduce the aperture jitter. A new bootstrapped MOS switch is designed in the sample and hold circuit to enhance the IF sampling capability. The ADC achieves a spurious free dynamic range (SFDR) of 67.1 dB, signal-to-noise ratio (SNDR) of 55.1 dB for a 10.1 MHz input, and SFDR of 61.6 dB, SNDR of 52.6 dB for a 355 MHz input at full sampling rate. Differential nonlinearity (DNL) is +0.5/−0.4 LSB and integral nonlinearity (INL) is +0.8/−0.75 LSB. Fabricated in a 0.18-μm 1P6M CMOS process, the prototype 10-bit pipelined ADC occupies 1.8 × 1.3 mm2 of active die area, and consumes only 68 mW at 1.8 V supply.

A 10-bit 25-MS/s 1.25-mW Pipelined ADC With a Semidigital Gm-Based Amplifier

A semidigital Gm-based amplifier is proposed for a low-power pipelined analog-to-digital converter (ADC). The amplifier performs a class-AB operation by smoothly changing between a comparator-like semidigital driver and a continuous-time high-gain amplifier according to the input voltage difference. A 10-bit pipelined ADC with 2.5-bit/stage architecture is implemented in a 0.13- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\mu\hbox{m}$</tex></formula> CMOS. The ADC consumes 1.25 mW at a sampling rate of 25 MS/s and achieves a Nyquist-rate figure-of-merit of 139 and 232 fJ/c-s without and with power consumption from a resistor ladder, respectively.

An 11.1 mW 42 MS/s 10 b ADC With Two-Step Settling in 0.18 $\mu$m CMOS

A pipelined analog-to-digital converter (ADC) uses switched-capacitor stages that settle in two steps that occur sequentially in time. The first step of settling places charge onto the load capacitance using charge pumps, and the second fulfills the settling requirements using typical negative feedback around an operational amplifier. Hence, the design combines the efficiency of a fast charge-transfer phase with the gain and noise-immunity advantages of amplifier-driven settling. Improved conversion efficiency results from a higher ratio of current delivered to the load to that consumed in static biasing. Additional circuitry constrains critical amplifier node voltages during the charge transfer, facilitating a graceful transition to amplifier-driven settling. The two-step settling technique is demonstrated in a 2.5 bit/stage 10-bit pipelined ADC that consumes 11.1 mW while sampling a 21.3 MHz input signal at 42 MS/s. The resulting SNDR is 55.6 dB (ENOB = 8.94) and the SFDR is 67.5 dB.

An Ultra-Energy-Efficient Wide-Bandwidth Video Pipeline ADC Using Optimized Architectural Partitioning

The classical pipeline analog-to-digital converter (ADC) architecture is analyzed to determine optimal partitioning for high effective resolution bandwidth (ERBW) and low-power consumption at reduced supply voltages. It is found that multibit inter-stage partitioning, in particular 2.5 bits per stage, is optimum for the reduction of power consumption in subsampling video ADCs for mobile/handheld receivers. To validate the analysis, a 1.5-V, 10-bit pipeline ADC for the digital video broadcast-handheld application was realized in a standard 3.3-V, 0.35-mum CMOS technology, with 2.5-2.5-2.5-4 partitioning employed. At the target sampling rate of 20.48 MS/s, measured results show that the converter achieves 56-dB SNR, 60-dB spurious-free dynamic range, 100-MHz ERBW and a power consumption of 19.5 mW. Energy consumption per conversion is only 0.19 pJ, making it the most energy-efficient 10-bit video-rate pipeline ADC reported to date

10-비트 200MS/s CMOS 병렬 파이프라인 아날로그/디지털 변환기의 설계

본 연구에서 매우 정밀한 샘플링을 필요로 하는 고해상도 비디오 응용면을 위하여 병렬 파이프라인 아날로그 디지털 변환기(ADC)를 설계하였다. 본 ADC의 구조는 4 채널의 10-비트 파이프라인 ADC를 병력 time-interleave로 구성한 구조로서 이 구조에서 채널 당 샘플링 속도의 4배인 200MS/s의 샘플링 속도를 얻을 수 있었다. 변환기에서 핵심이 되는 구성요소는 Sample and Hold 증폭기(SHA), 비교기와 연산증폭기이며 먼저 SHA를 전단에 설치하여 시스템 타이밍 요구를 완화시키고 고속변환과 고속 입력신호의 처리론 가능하게 하였다. ADC 내부 단들의 1-비트 DAC, 비교기 및 2-이득 증폭기는 한 개의 switched 캐패시터 회로로 통합하여 고속동작은 물론 저 전력소비가 가능한 특성을 갖도록 하였다. 본 연구의 연산증폭기는 2단 차동구조에 부저항소자를 사용하여 높은 DC 이득을 갖도록 보강하였다. 본 설계에서 각 단에 D-플립플롭(D-FF)을 사용한 지연회로를 구성하여 변환시 각 비트신호를 정렬시켜 타이밍 오차를 최소화하였다. 된 변환기는 3.3V 공급전압에서 280㎽의 전력소비를 갖고 DNL과 INL은 각각 +0.7/-0.6LSB, +0.9/-0.3LSB이다. This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.