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  • New
  • Research Article
  • 10.1016/j.mejo.2026.107064
Design and implementation of full adder using negative differential resistance circuits based on CMOS process
  • Apr 1, 2026
  • Microelectronics Journal
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A low-cost hardware-algorithm co-optimized architecture for sparse CNN acceleration on edge devices
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  • Microelectronics Journal
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  • New
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Design of image encryption and compression scheme compatible with JPEG XS based on spatial scrambling
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  • Microelectronics Journal
  • Yizhong Yang + 3 more

  • New
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A 97.7 dB-SNDR 1 MS/s power/bandwidth scalable exponential-incremental noise-shaping pipeline ADC
  • Apr 1, 2026
  • Microelectronics Journal
  • Tao Chen + 8 more

  • New
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A monolithic integrated quantum random number generation based on Band-to-Band tunneling effect
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  • Microelectronics Journal
  • Feiqiang Li + 8 more

  • New
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An FVF-CFFRC hybrid LDO for high PSR and fast transient response
  • Apr 1, 2026
  • Microelectronics Journal
  • Shangzheng Yang + 5 more

  • New
  • Research Article
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Single-event burnout hardening in p-GaN HEMTs through comb-patterned N-AlGaN channel engineering
  • Apr 1, 2026
  • Microelectronics Journal
  • Sheng Gao + 7 more

  • New
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Mechanism and pattern of Micro-Cu pillar array interconnection in electroplating bonding using a single-accelerator system
  • Apr 1, 2026
  • Microelectronics Journal
  • Yuting Zhong + 3 more

  • New
  • Research Article
  • 10.1016/j.mejo.2026.107074
A low-loss and compact three-conductor balun with compensated artificial asymmetric transmission line in InP technology
  • Apr 1, 2026
  • Microelectronics Journal
  • Yao Li + 5 more

  • New
  • Research Article
  • 10.1016/j.mejo.2026.107199
A 60V Chopper Amplifier Achieving 3μV VOS with Adaptive Input Bias Current Compensation
  • Apr 1, 2026
  • Microelectronics Journal
  • Jingbin Feng + 5 more