Despite advances in 2.5D and 3D packaging, ultrasonic wedge (stitch) bonding remains the industry standard due to its cost-effectiveness. However, the transition to copper (Cu) and palladium-coated copper (PCC) wire introduces reliability challenges, traditionally mitigated by expensive and environmentally concerning silver (Ag) plating on leadframes (LF). To address this, we developed a low-cost, ultrathin Cu-selective passivation coating that suppresses oxidation, enabling direct Cu-Cu bonding without Ag. This process-compatible coating was evaluated on Cu-LFs using 25 µm Al-1 wt% Si and PCC wires under varying thermal conditions (125 °C-200 °C). Optimization of bonding force, time, and ultrasonic power yielded substantial improvements in pull strength. Notably, while bare-Cu bonds failed at the oxidized interface, passivated samples failed at the wire neck, confirming superior bond integrity. This work highlights a promising, environmentally sustainable alternative to Ag plating, enabling reliable Cu-Cu stitch bonding for next-generation, low-cost IC packaging solutions.

This study reports, for the first time, the fully additive fabrication of miniaturized, embedded triple-stacked copper spiral inductors—an unprecedented achievement in multilayer inductor manufacturing. Using our novel Sequential Build-Up–Covalent Bonded Metallization (SBU–CBM) method, we demonstrate a etch-free, room-temperature process capable of producing complex 3D inductor architectures with sub-10 μm features and high vertical integration. Unlike conventional additive, subtractive or hybrid subtractive–additive techniques, the SBU–CBM method enables high-resolution laser-defined patterning, selective electroless copper deposition, and accurate optical alignment— eliminating the need for vacuum systems, chemical etching, or thermal sintering. The successful fabrication of three vertically interconnected spiral inductors through 10 μm copper microvias confirms the method’s unmatched capability in fabricating intricate multilayer geometries through a fully additive process. Optical microscopy and X-ray Computed Tomography (XCT) imaging validates the structural integrity, precise interlayer alignment, and continuous electrical connectivity across all layers. Critically, the method achieves uniform miniaturized copper strip widths of 10 μm, underscoring its strength in high-density packaging and next-generation integrated systems. This breakthrough establishes SBU–CBM as a transformative approach for realizing compact, high-performance, and scalable 3D embedded components in future electronic applications.

The continuous scaling of semiconductor devices, driven by Moore’s Law, demands advancements in interconnect technologies. Cu-to-Cu direct bonding has emerged as a critical solution for enabling ultra-fine pitch, high-density interconnections with superior electrical and thermal performance compared to traditional Cu-to-solder joints. This bonding method is pivotal for applications such as 3D integration, FOWLP, and 2.5D/3D packaging, supporting miniaturization, high-speed data transfer, and improved thermal management. However, Cu oxidation during processing presents a significant barrier, degrading bond integrity, increasing interfacial resistance, and complicating backend-of-line (BEOL) packaging integration. To address these challenges, we developed an ultra-thin (2–5 nm) Cu-selective oxide-suppression coating using standard industry-compatible techniques, including chemical vapor deposition (CVD) and liquid-phase deposition (LPD). The coating effectively prevents Cu oxidation during high-temperature thermal compression bonding (TCB) without requiring high-vacuum equipment or costly metal coatings, enabling scalability for heterogeneous packaging. RAIRS-QCM metrology validated the coating’s chemical stability and persistent oxidation resistance even after two months of ambient storage. Oxidation suppression efficiency of ~53% was confirmed by RAIRS characterization following an annealing at ~300°C in ambient air for 1 hour. Bonding evaluations were performed on 5 nm passivated Cu substrates under optimized bonding conditions. Shear testing revealed an average force of 40.7 ± 4.2 kgf/cm 2 , exceeding MIL-STD-883 requirements. Cross-sectional STEM confirmed a defect-free Cu-Cu bonded interface, while STEM-EDX analysis verified that the coating effectively suppressed oxidation without impeding Cu-to-Cu bonding. This work establishes the developed coating as a scalable, high-throughput solution to enhance Cu-to-Cu bonding reliability, enabling next-generation semiconductor packaging with improved electrical, mechanical, and thermal performance.

This paper presents a mechanical simulation of image sensor packages, with a particular emphasis on accurately modeling the cure shrinkage and viscoelasticity. Image sensors have a wide application in mobile phones, autonomous vehicles, and medical imaging. They are highly sensitive to warpage and misalignment, which can significantly degrade the image quality. The encapsulant acts as a primary barrier, protecting the sensor from external factors such as moisture and thermal mechanical stress. Accurately modeling and predicting the package warpage is crucial to ensure the optimal optical performance. Previous simulation studies on image sensor packaging often neglect cure shrinkage, leading to inaccurate warpage predictions. Cure shrinkage, a phenomenon where the material contracts during the curing process, can induce significant stress on the package and lead to warpage in addition to CTE-mismatch. This work developed a new simulation approach to incorporating cure shrinkage modeling, and it achieved a much higher degree of accuracy in predicting package warpage, as demonstrated by the close correlation between simulation results and actual warpage testing data. Furthermore, this paper studied the impact of using viscoelastic properties and compared time-dependent deformation with elastic solutions. Finally, this paper conducted comprehensive design of experiments (DOE) studies to evaluate the impact of different encapsulant materials on the susceptibility to glass cracking. The findings of this work are particularly useful for improved warpage prediction in simulation and better understanding of encapsulant properties, ultimately optimizing the package design and enhancing the reliability and longevity of electronic devices.

Gallium-based liquid metals (LMs) are materials that possess some unique properties. Just like any other metal, they have high thermal conductivity and low interfacial resistance, but they are in a liquid phase at room temperature. In contrast to mercury alloys, gallium alloys are non-toxic. They don’t evaporate and they can’t be inhaled. The viscosity of those alloys is very similar to water, but they are six times as dense as water. All those properties make Gallium-based liquid metals very good candidates for thermal interface material (TIM) in electronics applications. On the other hand, the reaction and incompatibility of those alloys with some metals is one of the challenges for this type of TIM. The other challenge is that those materials are not just thermally, but also electrically conductive and that is not a desirable property for TIM. A suitable barrier that will prevent any leakage of LMs and the best way to apply the appropriate volume of LM in high-volume production (HVP) would be one of the most important things for any application. A key challenge is applying the liquid metal consistently through a traditional dispensing method due to its property and behavior which involves high surface tension. Through advanced dispensing techniques like jetting technology liquid metal can be applied reliably on a flat, uneven surface or in arrays of minuscule confined spaces or cavities. This paper highlights the dispensing quality, weight repeatability from one substrate to another, and valve hardware stability. This paper will also address the challenges faced during dispensing of liquid metal in high volume manufacturing, and how to achieve desired bondline thickness with jet dispensing for higher throughput and process reliability.

There have been strong demands for lower power consumption and higher bandwidth in optical/electrical interconnects used for artificial intelligence (AI) and networks in a data center. The adoption of co-packaged optics (CPO) has been expected for both high-performance computing (HPC) driven by AI and high-bandwidth and high-speed communications networks in a data center. In this study, on-board optics (OBO), near package optics (NPO), and CPO will be discussed. Emphasis is placed on 3D heterogeneous integration of chiplets such as photonic integrated circuits (PIC), electronic integrated circuits (EIC), and application specific IC (ASIC) switch w/o bridges on CPO substrates, e.g., organic, silicon, and glass. Some recommendations will be provided.

Nanoporous silica waveguides can be used to improve the low sensitivity of near-infrared spectroscopic gas sensors by allowing the light propagating through the waveguide core to interact directly with molecules entering the pores. Here we report on a self-aligned fiber-to-waveguide configuration that offers a robust and cost-effective solution for coupling fibers to the nanoporous waveguide without the need for active alignment or expensive instrumentation. Our approach uses dedicated fiber-alignment structures next to the waveguide, fabricated at the same time as the waveguide, and made from the same material, thus eliminating the need for separate substrates, additional fabrication steps, and minimizing thermally induced optical misalignment. We present the optimized microfabrication process steps that allow for direct insertion of optical multimode silica fibers next to the multimode porous silica waveguide and provide structural and optical characterization. Gas sensing performance is evaluated using isopropyl alcohol vapor showing excellent sensitivity and detection limit of 1.76 ppm for a 10 mm long waveguide.

Buried cavities in low temperature co-fired ceramic (LTCC) substrates, whether completely blind or fabricated with ports, are often utilized in industry in areas such as microelectronics packaging, microfluidic sensor fabrication, and microwave resonant chamber creation. These applications often have stringent requirements for cavity volume, parallelism, and wall planarity that are critical for the performance of a given device. While there has been significant research and reporting on the fabrication and functionality of these structures, there is a lack of available literature regarding methods used to mitigate deformation of these structures during the fabrication process while providing for precise dimensional control of the final structure. Although essential processes in the fabrication of LTCC structures, the lamination and sintering steps both pose challenges to creating uniform and precise buried cavities in LTCC substrates: deformation due to high pressure on unsupported green tape structures during lamination, as well as volume loss and deformation during the sintering process. This paper will report on methods, technologies, and processes used to mitigate deformation and allow for precise and repeatable dimensional control of buried cavities in LTCC substrates. Specifically, fugitive materials and rigid cavity inserts will be used in conjunction with the manipulation of lamination pressures and sintering profiles to understand and control the forces resulting in the deformation of these buried cavity structures. The results of these technologies and processes will be examined through cross sectioning and optical inspection as well as through contact profilometry.

In this study, two problems of flip chip on glass-core package substrate will be investigated. The first problem deals with the flip chip on glass-core package substrate with microbumps and the other deals with the flip chip on glass-core package substrate with Cu-Cu hybrid bonding. Emphasis is placed on the solder joint reliability due to the glass-core substrate by nonlinear time and temperature dependent simulations, especially for the determination of the warpage of the structure and accumulated inelastic strain of the solder joints. Some recommendations will be provided.

Residual fluorine on Al wire bond pads of semiconductor wafers has been attributed to the reactive plasma etching of passivation dielectric layers during the bond pad opening process employing hydrofluorocarbon gases. Even though the initial fluorine concentration immediately after pad cleaning processes is typically below 5 at.%, the concentration can increase to a few times higher with prolonged wafer storage times. Higher fluorine concentrations on the Al bond pad surface increases the risk of aluminum fluoride crystal growth, resulting in pad discoloration. The impediment of intermetallic compound (IMC) formation during wire bonding caused by aluminum fluoride crystals on the Al bond pad surface acting as an interdiffusion barrier can lead to process, quality and reliability issues with the semiconductor device. Through this work, the mechanism of increase of fluorine concentration on Al bond pads, the mechanism of aluminum fluoride crystal formation, and the prevention methods are better understood. Transmission electron microscopy (TEM) analysis revealed that disruptions in the native Al2O3 layer underneath the aluminum fluoride crystal form paths for Al supply for the crystal formation and growth, forming depletion voids in the Al surface. The chemical composition of the aluminum fluoride crystals has been ascertained by X-ray photoelectron spectroscopy (XPS) to be AlF3. A detailed study of the effects of wafer storage methods on fluorine concentration on Al metallization of test wafers confirmed an outgassing-condensation mechanism occurring inside the wafer storage. Three storage-related factors have been found to influence the outgassing of fluorine compounds from the wafer polyimide passivation and condensation of fluorine compounds on the Al bond pads: humidity level, displacement of fluorine outgassing species by N2, and restriction of outgassing by wafer interleaf film. At the wafer fabrication site, storage of in-process wafers (in wafer box or wafer carrier) in a N2 cabinet shows a much higher effectiveness in reducing the fluorine compound condensation on the Al bond pads. At the packaging assembly site, the wafer canister storage methods (wafer canister sealed in moisture-barrier bag (MBB) with desiccant, and wafer canister in N2 cabinet) provide adequate protection for finished wafers from Al bond pad discoloration. These wafer storage methods have effectively prevented the occurrence of fluorine-induced Al bond pad discoloration over prolonged wafer storage times in both the wafer fabrication and packaging assembly sites.