An FMCW frequency synthesizer features fractional bandwidth boosting (FBWB), phase-noise correlation and cancellation, a digitally-controlled oscillator (DCO) with fast look-up table (LUT) initialization scheme, ultra-fast low-power MMD. With a bandwidth-boosting factor of 2.4, the prototype measures a continuous chirp fractional bandwidth (FBW) of 67.2%, frequency tuning range (FTR) of 111%, PN of −121.5dBc/Hz at 1MHz offset from 7.25GHz, jitter of 88 fs, and 0.06ms LUT convergence time while consuming 31.7 mW, corresponding to FOM<sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> of −204.7dB.

The growing incorporation of power electronic converter-based renewable energy sources, such as solar Photovoltaic (PV) systems, has introduced a new challenge to grid stability due to the complex control dynamics and intermittent nature of sources. In this article, an innovative stability monitoring approach based on Digital Twin (DT) technology is presented for a two stage three phase grid connected photovoltaic system. A DT using concept of state space model is developed for a two stage three phase grid connected photovoltaic system based on mathematical model using Tustin transformation. A newly developed Discrete Damping ratio Adaptation Second Order Generalized Integrator-Frequency Locked Loop (DDASOGI-FLL) based Sliding Mode-Model Predictive Control (SM-MPC) and Adaptive Golden ratio based Electromagnetic Field Optimization (AG-EFO) algorithm are used for optimal performance of the entire system. Furthermore, the stability of the system and control are monitored periodically based on developed DT using the direct Lyapunov stability method. The stability assessments are conducted under various dynamic conditions such as unbalance & disturbance in grid voltage and irradiation change. To validate the accuracy of the developed DT and control strategies, a laboratory-based experimental prototype is developed.

The Booth multiplier provides high-performance signed multiplication by encoding and decreasing partial products (PPs) generated using the radix-4 Booth algorithm. Although the radix-8 produces fewer PPs than the radix-4 and needs fewer adders to accumulate PPs, it is not fast because the odd multiples of the multiplicand are generated in a complex unit, and attaining a high performance is challenging. This work alleviates this issue using approximate designs. An approximate 4:2 compressor is proposed in which the inputs are encoded by the generation and propagation method for the reduction of faulty rows in the truth table. The compressor, radix-8 Booth encoder, and PP generation (PPG) are used to attain a signed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$16\times 16$</tex-math> </inline-formula>-bit, approximate multiplier, and synthesized targeting a 90 nm complementary metal oxide semiconductor (CMOS) technology. The multiplier is efficiently implemented on field programmable gate arrays (FPGAs) to perform the Sobel operator for edge detection. The occupied area, dynamic power dissipation, and power-delay-product (PDP)<inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $</tex-math> </inline-formula> mean relative error distance (MRED) of the presented multiplier are superior to the lookup table (LUT)-based multipliers of an FPGA. The Sobel edge detection algorithm implemented on the FPGA detects 99.15% of edges with 33.33% energy savings, while the structural similarity index measure (SSIM) and peak signal-to-noise ratio (PSNR) are 0.88 and 32.92dB, respectively.

This paper introduces a smart Digital Twin (DT) framework for a single-phase grid-integrated solar photovoltaic (SPV) inverter system that ensures advanced fault diagnostics and optimized operational performance. The DT is mathematically formalized using state-space equations modelling, functioning as a virtual counterpart to the physical system (PS). Real-time synchronization is achieved through high-fidelity sensor data acquisition within PS, enabling continuous monitoring and adaptive control. A rigorously formulated objective function, integrating empirical PS data and mathematically inferred parameters, underpins the optimization process, ensuring a superior digital representation. The critical system parameters, including ON-state resistance variations of switches, capacitance drifts, and inductor losses, are dynamically calibrated through an Electrostatic & Electromagnetic Field Discharge-Hybrid Optimization (E2FD-HO), a physics-driven optimization algorithm. The DT not only enables data-driven fault diagnostics but also proactively mitigates operational instabilities through real-time predictive control strategies. The control for the system is implemented within the FPGA-based controller (NI-sbRIO-9636) and the proposed DT framework is implemented on the OPAL-RT setup. The results of DT in comparison to hardware results of PS demonstrate an exceptional percentage matching score (PSM) of DT & PS, above than 98.5%, confirms its robustness and predictive precision. The developed DT offers a transformative approach to SPV inverter diagnosis, advancing circuit-level intelligence in smart energy systems.

Processing-in-memory (PIM) architectures alleviate memory bottlenecks and improve latency and energy efficiency for AI and ML workloads by accelerating general matrix-vector multiplication (GEMV) operations in DNNs. However, permanent faults in arithmetic units (AUs) within processing units (PUs) critically impact yield and inference accuracy. Although the hybrid built-in self-test (HBIST) method has been proposed, it has limited capabilities in diagnosing and repairing faulty AUs within PUs. In this study, a novel Self-Test And Repair structure for PIM (STAR-PIM) is proposed to enable both fault diagnosis and repair by incorporating a bypass mechanism. A scan-path-like approach enables the testing and precise localization of faulty AUs, while faulty adders are bypassed using a redundant adder structure integrated within the memory die. Furthermore, faulty multipliers are masked using the weight-swapping logic. Experimental results demonstrate that STAR-PIM achieves high AU-level test coverage, ranging from 98.89% to 100% with reasonable area overhead. Recovery experiments show that STAR-PIM maintains low relative errors under fault rates up to 1% for GPT-2 and preserves inference accuracy under fault rates up to 3% for MNIST-MLP. Power measurements on GDDR6-AiM indicate an average overhead of 7.39% with only a 0.08% latency increase. Consequently, STAR-PIM significantly enhances the yield and reliability of PIM while reducing test costs, making it a highly practical solution.

As the global energy structure shifts toward cleaner sources, wind power prediction has become increasingly important in modern energy management. Traditional prediction methods mainly rely on manual adjustment of model parameters and are constrained by hardware implementation conditions. The crossbar array structure of memristors can perform matrix operations directly in memory, offering significant energy efficiency advantages over traditional computing architectures. A hardware circuit design based on memristors for the improved red-billed blue magpie optimizer (IRBMO) and gate recurrent unit (GRU) is presented. The circuit includes the foraging module, the cooperation module, the mutation module and the GRU module. They realize the parallel computation of the prediction process. The circuit not only improves the computational efficiency, but also stores the optimal fitting value effectively. To further validate that the method is practical and effective, the simulation experiments are carried out in the short-term wind power prediction tasks. The results affirm the method high level of accuracy in short-term prediction tasks, which will provide a reference for the hardware implementation of neural network optimization.